ADCMP561 Analog Devices, ADCMP561 Datasheet

no-image

ADCMP561

Manufacturer Part Number
ADCMP561
Description
Manufacturer
Analog Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADCMP561BRQZ
Manufacturer:
AD
Quantity:
20 000
Preliminary Technical Data
FEATURES
Differential PECL compatible outputs
1 ns propagation delay input to output
100 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Input differential range
Robust input protection
Differential latch control
Power supply rejection greater than 70 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Dual High Speed PECL Comparators
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 1 ns propagation delay with less than 150 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP562.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to V
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation.
The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C). The ADCMP561 is
available in a 16-lead QSOP package. The ADCMP562 is
available in a 20-lead QSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
NONINVERTING
FUNCTIONAL BLOCK DIAGRAM
INVERTING
ADCMP561/ADCMP562
LATCH ENABLE
INPUT
INPUT
INPUT
© 2004 Analog Devices, Inc. All rights reserved.
Figure 1.
ADCMP561/
ADCMP562
LATCH ENABLE
INPUT
DD
Q OUTPUT
Q OUTPUT
− 2 V. A latch
www.analog.com

Related parts for ADCMP561

ADCMP561 Summary of contents

Page 1

... The ADCMP561/ADCMP562 are specified over the industrial temperature range (−40°C to +85°C). The ADCMP561 is available in a 16-lead QSOP package. The ADCMP562 is available in a 20-lead QSOP package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

Page 2

... ADCMP561/ADCMP562 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Considerations.............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Timing Information ......................................................................... 8 Application Information.................................................................. 9 Clock Timing Recovery ............................................................... 9 REVISION HISTORY Revision PrA: Initial Version Preliminary Technical Data Optimizing High Speed Performance ........................................9 Comparator Propagation Delay Dispersion ..............................9 Comparator Hysteresis .............................................................. 10 Minimum Input Slew Rate Requirement ...

Page 3

... Preliminary Technical Data SPECIFICATIONS ADCMP561/ADCMP562 Electrical Characteristics (V Table 1. Parameter 1 DC INPUT CHARACTERISTICS Input Common-Mode Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance ...

Page 4

... ADCMP561/ADCMP562 Parameter Equivalent Bandwidth Toggle Rate Minimum Pulse Width Unit-to-Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current Negative Supply Current Logic Supply Current Logic Supply Current Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Power Dissipation Power Dissipation Power Supply Sensitivity— ...

Page 5

... Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. ADCMP561/ADCMP562 Stress Ratings Parameter Supply Voltages Positive Supply Voltage (V to GND) CC Negative Supply Voltage (V to GND) EE Logic Supply Voltage (V to GND) DD Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls ...

Page 6

... ADCMP561/ADCMP562 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADCMP561 LEA 4 TOP VIEW LEA 5 (Not to Scale –INA 7 +INA 8 Figure 2. ADCMP561 16-Lead QSOP Pin Configuration Pin No. ADCMP561 ADCMP562 Mnemonic LEA 5 6 LEA ...

Page 7

... One of Two Complementary Inputs for Channel logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the description of Pin LEB for more information. Logic Supply Terminal. Rev. PrA | Page ADCMP561/ADCMP562 ...

Page 8

... ADCMP561/ADCMP562 TIMING INFORMATION LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Figure 4 shows the compare and latch features of the ADCMP561/ADCMP562. Table 3 describes the terms in the diagram. Table 3. Timing Descriptions Symbol Timing t Input to Output High Delay PDH t Input to Output Low Delay ...

Page 9

... The ADCMP561/ADCMP562 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP561/ADCMP562 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance ...

Page 10

... ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive condi- tions are changed (Figure 5). For the ADCMP561/ADCMP562, overdrive dispersion is typically 100 ps as the overdrive is changed from 100 This specification applies for both ...

Page 11

... ADCMP561/ADCMP562 V IN ADCMP561/ ADCMP562 V REF – ALL RESISTORS 50Ω Figure 10. Hysteresis Using Positive Feedback V IN ADCMP561/ ADCMP562 V – 2V 450Ω HYSTERESIS DD VOLTAGE ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED Figure 11. Hysteresis Using Latch Enable Input 50Ω ADCMP561 ADCMP562 50Ω ...

Page 12

... ADCMP561/ADCMP562 TYPICAL PERFORMANCE CHARACTERISTICS –5 +3 –000 –000 TBD –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) Figure 13. Input Bias Current vs. Input Voltage –000 –000 TBD –000 –000 –000 –000 –000 –000 ALL CAPS (Initial caps) Figure 14. Input Offset Voltage vs. Temperature – ...

Page 13

... Figure 22. Propagation Delay vs. Common-Mode Voltage –000 –000 –000 –000 –000 –000 –000 –000 –000 –000 Rev. PrA | Page ADCMP561/ADCMP562 TBD –000 –000 –000 ALL CAPS (Initial caps) TBD –000 –000 –000 ALL CAPS (Initial caps) Figure 23. Propagation Delay Error vs. Pulse Width – ...

Page 14

... COPLANARITY COPLANARITY ORDERING GUIDE Model Temperature Range ADCMP561BRQ −40°C to +85°C ADCMP562BRQ −40°C to +85°C © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04687–0–2/04(PrA) ...

Related keywords