LPC2387 NXP Semiconductors, LPC2387 Datasheet
LPC2387
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LPC2387 Summary of contents
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... Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2387 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with ...
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... Product data sheet 2 C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with Rev. 02 — 1 February 2008 LPC2387 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Type number Package Name LPC2387FBD100 LQFP100 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) Local bus LPC2387FBD100 512 64 LPC2387_2 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 SRAM (kB) Ether net Ethernet GP/ RTC Total buffers USB ...
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... AD0 A/D CONVERTER AOUT D/A CONVERTER VBAT 2 kB BATTERY RAM power domain 2 power domain 2 RTCX1 RTC RTCX2 OSCILLATOR WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2387 block diagram LPC2387_2 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 512 TEST/DEBUG FLASH INTERFACE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2387 pinning LQFP100 package 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 46 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 47 I/O SCL1 O I I/O [1] P0[2]/TXD0 98 I/O O [1] P0[3]/RXD0 99 I/O I [1] P0[4]/ 81 I/O I2SRX_CLK/ I/O RD2/CAP2[ LPC2387_2 Product data sheet 1 75 LPC2387FBD100 25 002aad329 Description Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
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... SCK — Serial clock for SPI. P0[16] — General purpose digital input/output pin. RXD1 — Receiver input for UART1. SSEL0 — Slave Select for SSP0. SSEL — Slave Select for SPI. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip 2 S-bus specification . 2 S-bus specification . ...
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... AD0[2] — A/D converter 0, input 2. I2SRX_SDA — Receive data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I TXD3 — Transmitter output for UART3. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip 2 S-bus specification . 2 S-bus specification . ...
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... It is HIGH when the device is not configured or during global suspend. PWM1[1] — Pulse Width Modulator 1, channel 1 output. CAP1[0] — Capture input for Timer 1, channel 0. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip 2 C-bus compliance). 2 C-bus compliance). ...
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... Port 2: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect block. Pins 14 through 31 of this port are not available. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. RXD2 — Receiver input for UART2. EXTIN0 — External Trigger Input. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... TMS — Test Mode Select for JTAG interface. TRST — Test Reset for JTAG interface. TCK — Test Clock for JTAG interface. This clock must be slower than clock (CCLK) for the JTAG interface to operate. Rev. 02 — 1 February 2008 LPC2387 Fast communication chip 2 S-bus specification . 2 S-bus specifi ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2387 being in Reset state. Note: This pin is available in LPC2387FBD100 devices only (LQFP package). ...
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... APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2387 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC and GPDMA controller ...
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... The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2387 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2387 includes a SRAM memory reserved for the ARM processor exclusive use ...
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... NXP Semiconductors 3.75 GB Fig 3. LPC2387 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2387 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...
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... The value of the output register may be read back as well as the current state of the port pins. LPC2387 uses accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...
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... Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2387 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access the USB SRAM not being used by the USB block ...
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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC2387 can enter one of the Power-down modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.12 10-bit ADC The LPC2387 contains one ADC single 10-bit successive approximation ADC with six channels. 7.12.1 Features • 10-bit successive approximation ADC. ...
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... UART3 includes an IrDA mode to support infrared communication. 7.15 SPI serial I/O controller The LPC2387 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... NXP Semiconductors 7.16 SSP serial I/O controller The LPC2387 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data fl ...
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... C2 use standard I/O pins and do not support powering off of individual 2 C-bus can be used for test and diagnostic purposes interface on the LPC2387 provides a separate transmit Rev. 02 — 1 February 2008 Fast communication chip S connection has one master, which is always the 2 S input and output). ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2387. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... Features • LPC2387 has one PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow single edge controlled or 3 double edge controlled PWM outputs mix of both types. The match registers also allow: – ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2387, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... NXP Semiconductors Upon power-up or any chip reset, the LPC2387 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.24.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... Power control The LPC2387 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value ...
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... When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.24.4.4 Power domains The LPC2387 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. The 3 These pins provide the power for the CPU and most of the peripherals ...
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... Code security (Code Read Protection - CRP) This feature of the LPC2387 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...
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... ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts. 7.26 Emulation and debugging The LPC2387 supports emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2387 contains a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...
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... V DD(3V3) supply voltage is present [2][3] other I/O pins [4] per supply pin [4] per ground pin [5] based on package heat transfer, not device power consumption [6] human body model; all pins Rev. 02 — 1 February 2008 LPC2387 Fast communication chip Min Max Unit 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V ...
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... [ [ 0 DD(3V3 DDA [ [8] V < V < DD(3V3) I Rev. 02 — 1 February 2008 LPC2387 Fast communication chip [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3.3 V DDA - - 100 DD(3V3) 2.0 ...
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... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz V = 3.3 V; DD(DCDC)(3V3 amb DC-to-DC converter on DC-to-DC converter off OLS DD(3V3 Rev. 02 — 1 February 2008 LPC2387 Fast communication chip [1] Min Typ Max - 125 - - ...
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... DD(3V3 and D . Conditions Rev. 02 — 1 February 2008 Fast communication chip [1] Min Typ - - - - 0.2 - 0 [11 1.1 - Min Typ [1][2][ [1][ [1][ LPC2387 Max Unit 2.5 V 2.0 V 0. 44.1 1.9 k Max Unit V V DDA LSB 2 LSB 3 LSB © NXP B.V. 2008. All rights reserved ...
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... Figure 4. Figure Figure 4. Rev. 02 — 1 February 2008 Fast communication chip Min Typ [1][ [1][ [ LPC2387 Max Unit 0 LSB 40 k Figure 4. © NXP B.V. 2008. All rights reserved ...
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... LSB (ideal (LSB ) IA ideal ). D ). Rev. 02 — 1 February 2008 Fast communication chip (1) 1018 1019 1020 1021 1022 1023 V V DDA SSA 1 LSB = 1024 LPC2387 offset gain error error 1024 002aac046 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors AD0[y] Fig 5. Suggested ADC interface - LPC2387 AD0[y] pin LPC2387_2 Product data sheet LPC2XXX 20 k SAMPLE Rev. 02 — 1 February 2008 LPC2387 Fast communication chip R vsi AD0[y] V EXT 002aac733 © NXP B.V. 2008. All rights reserved ...
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... EOP; see Figure 7 must accept as EOP; see Figure 7 over specified ranges. DD(3V3) Conditions amb measured in SPI Master mode; see Figure 8 Rev. 02 — 1 February 2008 LPC2387 Fast communication chip Min Typ Max 8.5 - 13.8 7 109 1.3 - 2.0 160 - 175 2 ...
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... SE0/EOP skew PERIOD FDEOP t su(SPI_MISO) Rev. 02 — 1 February 2008 Fast communication chip t CHCX t CLCH T cy(clk) 002aaa907 extended source EOP width: t receiver EOP width: t sampling edges 002aad326 LPC2387 FEOPT , t EOPR1 EOPR2 002aab561 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC23XX Fig 9. LPC2387 USB interface on a self-powered device LPC23XX Fig 10. LPC2387 USB interface on a bus-powered device LPC2387_2 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D DD(3V3) ...
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... REFERENCES JEDEC JEITA MS-026 Rev. 02 — 1 February 2008 Fast communication chip detail 0.75 1.15 1 0.2 0.08 0.08 0.45 0.85 EUROPEAN PROJECTION LPC2387 SOT407 ( 0.85 0 ISSUE DATE 00-02-01 03-02-20 © NXP B.V. 2008. All rights reserved ...
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... Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 02 — 1 February 2008 LPC2387 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Product data sheet Data sheet status Product data sheet 3: Pin description for RSTOUT changed from “This is a 1.8 V pin.” to “This is a 3.3 V Product data sheet Rev. 02 — 1 February 2008 LPC2387 Fast communication chip Change notice Supersedes - LPC2387_1 - - © NXP B.V. 2008. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 1 February 2008 LPC2387 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2387 All rights reserved. Date of release: 1 February 2008 Document identifier: LPC2387_2 ...