74LVC125APW,118 NXP Semiconductors, 74LVC125APW,118 Datasheet - Page 9
![IC BUFF DVR TRI-ST QD 14TSSOP](/photos/6/58/65814/568-14-tssop_sot402-1_sml.jpg)
74LVC125APW,118
Manufacturer Part Number
74LVC125APW,118
Description
IC BUFF DVR TRI-ST QD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC125ABQ115.pdf
(20 pages)
Specifications of 74LVC125APW,118
Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 24 mA
Input Bias Current (max)
40 uA
Low Level Output Current
24 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.4 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Logical Function
Buffer/Line Driver
Number Of Elements
4
Number Of Channels
4
Number Of Inputs
4
Number Of Outputs
4
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Package Type
TSSOP
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.2V
Quiescent Current
40uA
Technology
CMOS
Pin Count
14
Mounting
Surface Mount
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2288-2
74LVC125APW-T
935231720118
74LVC125APW-T
935231720118
Philips Semiconductors
AC WAVEFORMS
2003 May 07
handbook, full pagewidth
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
V
V
V
V
V
V
V
V
V
M
M
OL
M
M
X
X
Y
Y
= V
= V
= V
= V
= 1.5 V at V
= 0.5V
= 1.5 V at V
= 0.5V
and V
OL
OL
OH
OH
+ 0.3 V at V
+ 0.1 V at V
+ 0.3 V at V
+ 0.1 V at V
CC
CC
OH
at V
at V
are typical output voltage drop that occur with the output load.
CC
CC
CC
CC
< 2.7 V;
< 2.7 V;
2.7 V;
2.7 V;
CC
CC
CC
CC
< 2.7 V;
< 2.7 V.
2.7 V;
2.7 V;
HIGH-to-OFF
OFF-to-HIGH
OFF-to-LOW
LOW-to-OFF
nOE input
output
output
handbook, halfpage
Fig.6 The input nA to output nY propagation delays.
V
OL
nY output
nA input
and V
GND
GND
V OH
V CC
V OL
V I
Fig.7 3-state enable and disable times.
OH
GND
are typical output voltage drop that occur with the output load.
V OH
V OL
V I
V M
enabled
outputs
t PLZ
t PHZ
V M
V X
9
V M
V Y
t PHL
disabled
outputs
t PZL
t PZH
MNA230
t PLH
V M
V M
outputs
enabled
MNA362
Product specification
74LVC125A