74LVCH244APW,112 NXP Semiconductors, 74LVCH244APW,112 Datasheet - Page 4

• Manufacturer Part Number: 74LVCH244APW,112
• Description: IC BUFF/DVR TRI-ST DUAL 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCHr

Specifications of 74LVCH244APW,112

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 4
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Logic Family: LVC
• Logical Function: Buffer/Line Driver
• Number Of Elements: 2
• Number Of Channels: 8
• Number Of Inputs: 8
• Number Of Outputs: 8
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: TSSOP
• Output Type: 3-State
• Polarity: Non-Inverting
• Propagation Delay Time: 11ns
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.2V
• Quiescent Current: 40uA
• Technology: CMOS
• Pin Count: 20
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVCH244APW; 74LVCH244APW; 935210350112

NXP Semiconductors
5. Pinning information
Table 2.
74LVC_LVCH244A_6
Product data sheet
Symbol
1OE, 2OE
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2A0, 2A1, 2A2, 2A3
1Y0, 1Y1, 1Y2, 1Y3,
V
Fig 4.
CC
Pin configuration for SO20 and (T)SSOP20
GND
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
Pin description
10
1
2
3
4
5
6
7
8
9
5.1 Pinning
5.2 Pin description
Pin
1, 19
2, 4, 6, 8
3, 5, 7, 9
10
17, 15, 13, 11 data input
18, 16, 14, 12 data output
20
74LVCH244A
74LVC244A
001aad113
Description
output enable input (active low)
data input
data output
ground (0 V)
supply voltage
20
19
18
17
16
15
14
13
12
11
V
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2A3
CC
Rev. 06 — 13 August 2009
74LVC244A; 74LVCH244A
Fig 5.
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Pin configuration for DHVQFN20 and
DHXQFN20U
index area
terminal 1
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
Transparent top view
2
3
4
5
6
7
8
9
Octal buffer/line driver; 3-state
74LVCH244A
74LVC244A
GND
(1)
19
18
17
16
15
14
13
12
001aad114
© NXP B.V. 2009. All rights reserved.
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
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