74LVC2G125DP,125 NXP Semiconductors, 74LVC2G125DP,125 Datasheet - Page 9
![IC BUS BUFF DVR TRI-ST DL 8TSSOP](/photos/5/43/54394/8-tssop_sot505-2_pkg_sml.jpg)
74LVC2G125DP,125
Manufacturer Part Number
74LVC2G125DP,125
Description
IC BUS BUFF DVR TRI-ST DL 8TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2G125DC125.pdf
(22 pages)
Specifications of 74LVC2G125DP,125
Package / Case
8-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
40 uA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.7 ns (Typ) @ 2.7 V or 2.3 ns (Typ) @ 3 V to 3.6 V or 1.9 ns (Typ) @ 4.5 V to 5.5 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC2G125DP-G
74LVC2G125DP-G
935272175125
74LVC2G125DP-G
935272175125
NXP Semiconductors
12. Waveforms
Table 9.
74LVC2G125
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 7.
Fig 8.
CC
Measurement points are given in
Logic levels: V
Propagation delay input (nA) to output (nY)
Measurement points are given in
Logic levels: V
3-state output enable and disable times
Measurement points
OL
OL
Input
V
0.5V
0.5V
1.5 V
1.5 V
0.5V
and V
and V
M
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
CC
CC
CC
OH
OH
nOE input
output
output
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
nY output
nA input
GND
GND
V
V
V
Table
Table
OH
CC
OL
V
All information provided in this document is subject to legal disclaimers.
I
9.
9.
GND
V
V
OH
OL
V
Rev. 11 — 9 September 2010
I
Output
V
0.5V
0.5V
1.5 V
1.5 V
0.5V
V
M
M
enabled
outputs
t
PLZ
t
PHZ
CC
CC
CC
V
M
V
V
X
M
V
t
PHL
Y
disabled
outputs
V
V
V
V
V
V
X
OL
OL
OL
OL
OL
t
PZL
t
+ 0.15 V
+ 0.15 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
PZH
mna230
t
PLH
Dual bus buffer/line driver; 3-state
V
M
V
M
outputs
enabled
mna362
74LVC2G125
V
V
V
V
V
V
Y
OH
OH
OH
OH
OH
© NXP B.V. 2010. All rights reserved.
− 0.15 V
− 0.15 V
− 0.3 V
− 0.3 V
− 0.3 V
9 of 22