74LVC2G241GD,125 NXP Semiconductors, 74LVC2G241GD,125 Datasheet - Page 9

• Manufacturer Part Number: 74LVC2G241GD,125
• Description: IC BUFF DVR TRI-ST DL INV 8XSON
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC2G241GD,125

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 8-XSON
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: LVC
• Number Of Channels Per Chip: 2
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 32 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 2.8 ns (Typ) @ 2.7 V
• Number Of Lines (input / Output): 2 / 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC2G241GD-G; 74LVC2G241GD-G; 935286856125

NXP Semiconductors
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
[2]
[3]
[4]
[5]
12. Waveforms
Table 9.
74LVC2G241
Product data sheet
Symbol Parameter
C
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 7.
CC
PD
Typical values are measured at nominal V
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
Σ(C
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
power dissipation
capacitance
Measurement points are given in
Logic levels: V
The data input (nA) to output (nY) propagation delays
PD
Dynamic characteristics
Measurement points
CC
× V
2
× f
CC
o
2
) = sum of outputs.
× f
PLH
PZH
PLZ
i
× N + Σ(C
OL
and t
and t
and t
and V
PHL
PZL
PHZ
Conditions
per buffer; V
OH
L
.
.
.
output enabled
output disabled
× V
are typical output voltage levels that occur with the output load.
CC
nY output
nA input
Input
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
2
…continued
M
× f
Table
CC
o
All information provided in this document is subject to legal disclaimers.
I
) where:
= GND to V
and at T
CC
CC
CC
9.
GND
V
V
OH
OL
V
I
Rev. 10 — 6 August 2010
amb
CC
= 25 °C.
D
V
in μW).
M
Output
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
[5]
V
M
M
t
PHL
Figure
CC
CC
CC
Min
-
-
−40 °C to +85 °C
10.
Typ
20
5
V
V
V
V
V
V
mna230
[1]
t
X
OL
OL
OL
OL
OL
PLH
+ 0.15 V
+ 0.15 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
Dual buffer/line driver; 3-state
Max
-
-
74LVC2G241
−40 °C to +125 °C Unit
Min
-
-
V
V
V
V
V
V
© NXP B.V. 2010. All rights reserved.
Y
OH
OH
OH
OH
OH
− 0.15 V
− 0.15 V
− 0.3 V
− 0.3 V
− 0.3 V
Max
-
-
pF
pF
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