74AUP2G126GT,115 NXP Semiconductors, 74AUP2G126GT,115 Datasheet - Page 16
![IC BUFF DVR 3-ST DL L PWR 8XSON](/photos/6/94/69486/8-xson_sml.jpg)
74AUP2G126GT,115
Manufacturer Part Number
74AUP2G126GT,115
Description
IC BUFF DVR 3-ST DL L PWR 8XSON
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet
1.74AUP2G126DC125.pdf
(24 pages)
Specifications of 74AUP2G126GT,115
Package / Case
8-XSON
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
0.5 uA
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
18.7 ns @ 1.1 V to 1.3 V or 10.8 ns @ 1.4 V to 1.6 V or 8.4 ns @ 1.65 V to 1.95 V or 6.3 ns @ 2.3 V to 2.7 V or 5.8 ns @ 3 V to 3.6 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP2G126GT-G
74AUP2G126GT-G
935280731115
74AUP2G126GT-G
935280731115
NXP Semiconductors
Fig 12. Package outline SOT1089 (XSON8)
74AUP2G126
Product data sheet
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
mm
SOT1089
Unit
Outline
version
max
nom
min
A
0.5
(1)
0.04
A
terminal 1
index area
terminal 1
index area
1
0.20
0.15
0.12
(4×)
b
IEC
b
(2)
1.40
1.35
1.30
4
1
D
1.05
1.00
0.95
E
L
1
0.55 0.35
MO-252
JEDEC
e
All information provided in this document is subject to legal disclaimers.
E
e
e
1
References
L
0
0.35
0.30
0.27
Rev. 06 — 21 June 2010
L
5
8
0.40
0.35
0.32
L
1
JEITA
e
D
1
scale
0.5
A
1 mm
(8×)
Low-power dual buffer/line driver; 3-state
A
(2)
1
detail X
European
projection
X
74AUP2G126
© NXP B.V. 2010. All rights reserved.
Issue date
10-04-09
10-04-12
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