74LVT16245BDL,118 NXP Semiconductors, 74LVT16245BDL,118 Datasheet - Page 4

IC TRANSCVR TRI-ST 16BIT 48SSOP

74LVT16245BDL,118

Manufacturer Part Number
74LVT16245BDL,118
Description
IC TRANSCVR TRI-ST 16BIT 48SSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT16245BDL,118

Logic Type
Transceiver, Non-Inverting
Package / Case
48-SSOP
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
74LVT
Number Of Channels Per Chip
16
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
1.9 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Function
Bus Transceiver
Input Bias Current (max)
6000 uA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Polarity
Non-Inverting
Number Of Circuits
8
Operating Supply Voltage (typ)
3.3V
Number Of Elements
2
Number Of Channels
16
Input Logic Level
LVTTL
Output Logic Level
LVTTL
Package Type
SSOP
Logical Function
Bus Transceiver
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Quiescent Current (typ)
4.7mA
Technology
BiCMOS
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVT16245BDL-T
74LVT16245BDL-T
935179190118
NXP Semiconductors
5. Pinning information
74LVT_LVTH16245B_7
Product data sheet
Fig 3. Pin configuration for SSOP48 and TSSOP48
1DIR
2DIR
GND
GND
GND
GND
V
V
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
CC
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
5.1 Pinning
74LVTH16245B
74LVT16245B
001aae471
All information provided in this document is subject to legal disclaimers.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Rev. 07 — 29 March 2010
1OE
1A0
1A1
GND
1A2
1A3
V
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
V
2A4
2A5
GND
2A6
2A7
2OE
74LVT16245B; 74LVTH16245B
CC
CC
Fig 4. Pin configuration for VFBGA56
G
A
B
C
D
E
F
H
K
J
1DIR
2DIR
1B1
1B3
1B5
1B7
2B0
2B2
2B4
2B6
1
1B0
1B2
1B4
1B6
2B1
2B3
2B5
2B7
n.c.
n.c.
2
Transparent top view
3.3 V 16-bit transceiver; 3-state
74LVT16245B
GND
GND
GND
GND
V
V
n.c.
n.c.
3
CC
CC
GND
GND
GND
GND
V
V
n.c.
n.c.
4
CC
CC
1A0
1A2
1A4
1A6
2A1
2A3
2A5
2A7
n.c.
n.c.
5
© NXP B.V. 2010. All rights reserved.
001aae474
1OE
2OE
1A1
1A3
1A5
1A7
2A0
2A2
2A4
2A6
6
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