74ALVCH16652DGG,11 NXP Semiconductors, 74ALVCH16652DGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16652DGG,11
• Description: IC 16BIT TXRX/REGISTER 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16652DGG,11

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16652DG-T; 74ALVCH16652DG-T; 935262799118

Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCP
and nS
inputs.
QUICK REFERENCE DATA
Ground = 0; T
Notes
1. C
2. The condition is V
1999 Nov 23
t
f
C
C
PHL
max
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50
Current drive 24 mA at 3.0 V.
SYMBOL
I
PD
16-bit transceiver/register with dual enable; 3-state
P
f
C
f
V
i
o
/t
AB
D
CC
PD
= input frequency in MHz;
L
(C
PLH
= output frequency in MHz;
BA
= output load capacitance in pF;
= C
or nCP
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
) or output enable (nOE
PD
V
CC
amb
BA
propagation delay nA
maximum clock frequency
input capacitance
power dissipation capacitance per latch
V
2
) regardless of the select inputs (nS
CC
flow-through pin-out architecture
= 25 C; t
f
2
o
) = sum of outputs.
I
f
= GND to V
i
+
r
= t
(C
transmission lines at 85 C
L
f
PARAMETER
= 2.5 ns.
AB
V
CC
and nOE
CC
n
.
, nB
2
n
f
o
to nB
) where:
BA
) control
n
, nA
AB
n
2
Depending on the select inputs nS
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOE
operation mode of the transceiver. When nOE
no data transmission from nB
nOE
possible.
When nS
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOE
nOE
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
D
C
notes 1 and 2
in W).
L
outputs enabled
outputs disabled
BA
BA
= 50 pF; V
. In this configuration each output reinforces its
is HIGH, no data transmission from nB
CONDITIONS
AB
and nS
CC
= 3.3 V
BA
are in the real-time transfer mode, it
n
AB
2.6
350
4.0
22
4.0
to nA
74ALVCH16652
TYPICAL
and nOE
AB
Product specification
n
is possible and when
and nS
BA
determine the
ns
MHz
pF
pF
pF
BA
AB
n
data can
to nA
UNIT
AB
is LOW,
and
n
is