IDT74LVC16501APAG8 IDT, Integrated Device Technology Inc, IDT74LVC16501APAG8 Datasheet
IDT74LVC16501APAG8
Manufacturer Part Number
IDT74LVC16501APAG8
Description
IC REGISTERED TXRX 3ST 56TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74LVCr
Datasheet
1.IDT74LVC16501APAG8.pdf
(6 pages)
Specifications of IDT74LVC16501APAG8
Logic Type
Registered Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
18
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC16501APAG8
FEATURES:
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©
FUNCTIONAL BLOCK DIAGRAM
IDT74LVC16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
machine model (C = 200pF, R = 0)
2006 Integrated Device Technology, Inc.
CC
CC
CLKBA
CLKAB
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
OEAB
OEBA
LEBA
LEAB
SK(o)
A
1
(Output Skew) < 250ps
1
30
28
27
55
3
2
3.3V CMOS 18-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
TO 17 OTHER CHANNELS
C
D
D
C
1
DESCRIPTION:
This high-speed, low power 18-bit registered bus transceiver combines D-
type latches and D-type flip-flops to allow data flow in transparent, latched,
and clocked modes. Data flow in each direction is controlled by output-
enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock
(CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A
bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.
OEAB performs the output enable function on the B port. Data flow from B
port to A port is similar but requires using OEBA, LEBA and CLKBA. Flow-
through organization of signal pins simplifies layout. All inputs are designed
with hysteresis for improved noise margin.
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16501A is built using advanced dual metal CMOS technology.
The LVC16501A has been designed with a ±24mA output driver. This
Inputs can be driven from either 3.3V or 5V devices. This feature allows
C
D
D
C
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16501A
JUNE 2006
54
B
1
DSC-4481/6
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IDT74LVC16501APAG8 Summary of contents
Page 1
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER FEATURES: • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF • 3.3V ± 0.3V, ...
Page 2
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER PIN CONFIGURATION 1 OEAB 2 LEAB GND GND ...
Page 3
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER FUNCTION TABLE (1,2) Inputs OEAB LEAB CLKAB ↑ ↑ NOTES HIGH Voltage ...
Page 4
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS ...
Page 5
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ V ...
Page 6
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER ORDERING INFORMATION X XX IDT XX LVC Bus-Hold Family Temp. Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXXX Device Type Package PV Shrink Small Outline Package PVG SSOP ...