IDT74FCT163244APAG IDT, Integrated Device Technology Inc, IDT74FCT163244APAG Datasheet - Page 5
![IC BUFF DVR 16BIT N-INV 48TSSOP](/photos/28/16/281686/48-tssop_pkg_sml.jpg)
IDT74FCT163244APAG
Manufacturer Part Number
IDT74FCT163244APAG
Description
IC BUFF DVR 16BIT N-INV 48TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74FCTr
Datasheet
1.IDT74FCT163244CPAG.pdf
(6 pages)
Specifications of IDT74FCT163244APAG
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
8mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Logic Family
FCT
Logical Function
Buffer/Line Driver
Number Of Elements
4
Number Of Channels
16
Number Of Inputs
16
Number Of Outputs
16
Operating Supply Voltage (typ)
3.3V
Package Type
TSSOP
Output Type
3-State
Polarity
Non-Inverting
Propagation Delay Time
6.2ns
High Level Output Current
-8mA
Low Level Output Current
24mA
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Quiescent Current
10uA
Technology
CMOS
Pin Count
48
Mounting
Surface Mount
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74FCT163244APAG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT74FCT163244APAG
Manufacturer:
IDT
Quantity:
20 000
TEST CIRCUITS AND WAVEFORMS
IDT74FCT163244A/C
3.3V CMOS 16-BIT BUFFER/LINE DRIVER
ASYNCHRONOUS CONTROL
Generator
SYNCHRONOUS CONTROL
Pulse
CLOCK ENABLE
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
PRESET
SAME PHASE
PRESET
TIMING
CLEAR
CLEAR
V
INPUT
OUTPUT
INPUT
DATA
IN
ETC.
ETC.
Set-up, Hold, and Release Times
Test Circuits for All Outputs
R
T
Propagation Delay
D.U.T
.
V
CC
t
PLH
t
PLH
t
t
SU
SU
V
OUT
t
REM
t
C
H
50pF
t
t
L
PHL
PHL
t
H
500
Ω
500
Ω
V
V
1.5V
1.5V
1.5V
3V
0V
3V
0V
Open
GND
OH
OL
3V
1.5V
3V
1.5V
3V
1.5V
0V
0V
3V
1.5V
0V
0V
6v
5
DEFINITIONS:
C
R
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
3. if V
SWITCH POSITION
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
CC
LOW-HIGH-LOW
OUTPUT
OUTPUT
is below 3V, input voltage swings should be adjusted not to exceed V
INPUT
All Other Tests
HIGH
Disable High
Disable Low
Enable High
LOW
Enable Low
Open Drain
Test
PULSE
PULSE
SWITCH
SWITCH
GND
ENABLE
Enable and Disable Times
6V
t
t
PZH
PZL
Pulse Width
INDUSTRIAL TEMPERATURE RANGE
1.5V
1.5V
3V
0V
t
PHZ
OUT
t
F
W
≤ 2.5ns; t
of the Pulse Generator.
DISABLE
t
PLZ
Switch
GND
Open
6V
R
≤ 2.5ns.
0.3V
0.3V
V
3V
1.5V
0V
3V
V
0V
OL
OH
1.5V
1.5V
CC
.