HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet
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HFA3861AIN
Related parts for HFA3861AIN
HFA3861AIN Summary of contents
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... The HFA3861A is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HFA3861AIN - TQFP HFA3861AIN96 - Tape and Reel Pinout GNDd DDD SD 3 SCLK ...
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Typical Application Diagram AntSel HFA3683A RF/IF CONV (FILE# 4634) Σ PLL RF LO REF IN HFA3963 RFPA (FILE# 4635) 44MHz MCLK T/Rsw DIFFERENTIAL SIGNALS For additional information on the PRISM® chip set, visit our web site www.intersil.com or call 1-888-INTERSIL ...
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Pin Descriptions NAME PIN TYPE I/O V (Analog) 12, 17, 22, Power DDA 31 V (Digital 37, 57 Power DDD GNDa 9, 15, 20, Ground (Analog) 25, 28, GNDd (Digital 36, 43, Ground ...
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Pin Descriptions (Continued) NAME PIN TYPE I/O MD_RDY 54 O RX_PE I/O SCLK 4 I SDI TEST 7:0 51, 50, 49, I/O 48, 47, 46, 45, 44 RESET ...
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HFA3861A AGC RXI ANALOG TXI RXQ INPUTS TXQ AGC TXD V A/D REF TXCLK REFERENCE I REF TX_RDY RXD TX_PE POWER RXC DOWN RX_PE MD_RDY SIGNALS RESET TEST TEST PORT SCLK R/W ANT_SEL SDI FIGURE 1. EXTERNAL ...
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TX Port The transmit data port accepts the data that needs to be transmitted serially from an external data source. The data is modulated and transmitted as soon received from the external data source. The serial data ...
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RXCLK RX_PE PROCESSING PREAMBLE/HEADER MD_RDY RXD NOTE: MD_RDY active after CRC16. See detailed timing diagrams (Figures 18, 19, 20). RXCLK is an output from the HFA3861A and is the clock for the serial demodulated data on RXD. MD_RDY is an ...
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Test Port The HFA3861A provides the capability to access a number of internal signals and/or data through the Test port, pins TEST 7:0. The test port is programmable through configuration register (CR 34). Any signal on the test port can ...
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MODE RX_PE TX_PE RESET STANDBY Inactive Inactive Inactive TX Inactive Active Inactive RX Active Inactive Inactive NO CLOCK I Standby Active CC TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz DATA A/D SAMPLE CLOCK MODULATION (MHz) DBPSK 22 ...
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This sequence is then modulated on the I and Q outputs. The initial phase reference for the data portion of the packet is the phase of the last bit of the header. At ...
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Some dummy bits will be appended to the end of the packet to insure an orderly shutdown of the transmitter. This prevents spectrum splatter. At the end of a packet, the external controller is ...
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Scrambling is done by a division using a prescribed polynomial as shown in Figure 9. A shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register. ...
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TABLE 5. DQPSK ENCODING TABLE EVEN SYMBOLS DIBIT PATTERN (d(0), d(1)) PHASE CHANGE ω) d(0) IS FIRST IN TIME (+ π π 11 π π /2) TABLE 6. 5.5Mbps CCK ENCODING TABLE ...
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An initial value of the noise floor is established within 50µs of the chip being active and is refined as goes on. Deasserting RX_PE does not corrupt the learned values. If the absolute power metric is chosen, this ...
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In the 1Mbps DBPSK mode, data demodulation is performed the same as in header processing. In the 2Mbps DQPSK mode, the demodulator demodulates two bits per symbol and differentially ...
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V (ANALOG) DD (12, 17, 22, 31) I (21) REF V (16) REF 6-BIT TX_AGC_IN (18) ADC 6-BIT TX_IF_AGC (35) DAC ANTSEL (39) ANTSEL (40) (62) TX_PE FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION PN Correlators Description There are two ...
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The biggest picker finds the biggest correlator outputs depending on the rate. This is translated into bits. The detected output is ...
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V (ANALOG) DD (12, 17, 22, 31) RX_IF_DET (19) RX_IF_AGC (34) 6-BIT RX-RF-AGC (38) DAC 6-BIT RXI (10, 11) A/D 6 6-BIT RXQ (13, 14) A/D 6 ANTENNA ANTSEL (40) SWITCH ANTSEL (39) CONTROL GENERATOR (63) RESET FIGURE 13. DSSS ...
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Data Demodulation in the CCK Modes In this mode, the demodulator uses Complementary Code Keying (CCK) modulation for the two highest data rates slaved to the low rate processor which it depends on for acquisition of initial timing ...
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Eb/ BER 2.0 THY 1, 2 FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES Clock Offset Tracking Performance The PRISM baseband processor is designed to accept data clock offsets ±25ppm for each ...
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A Default Register Configuration The registers in the HFA3861A are addressed with 7-bit numbers where the lower 1 bit of an 8-bit hexadecimal address is left as unused. This results in the addresses being in increments shown ...
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TABLE 9. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY (Continued) CONFIGURATION REGISTER CR40 Threshold for antenna decision CR41 Preamble tracking loop lead coefficient CR42 Preamble tracking loop lag coefficient CR43 Header tracking loop lead coefficient CR44 Header tracking loop lag ...
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Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 0001 = HFA3861A series Bit 3:0 Version ...
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CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD Bits 7:4 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 3 Select preamble mode 0 = Normal, long preamble interoperable with ...
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CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE (Continued) Bits 5:4 SFD Time-out values 00 = 56µ 64µ 128µ 144µs Bit 3 MD_RDY control 0 = After CRC16 1 = After SFD Bit 2 ...
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CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued) bit 0 Q A/D clock 0 = enable 1 = disable CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2 Bit 7 Standby 1 = enable 0 = ...
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CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC CONTROL 2 Bits 7:4 AGC mid Sat counts (0-15 range) these are the counts to kick in the attenuator steps (CR28). Bits 3:0 AGC low Sat Count (0-15 range) CONFIGURATION REGISTER 17 ADDRESS ...
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CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES Bits 7 AGC continuous update 0 = disable 1 = allow updates during freeze AGC and AGClock. CR26 bit 3 must be a ‘1’ for this mode to work. Bit 6 ...
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CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1 Bit 7 Selection bit for DAC input test mode Barker 1 = Low rate I/Q samples Bit 6 force high rate mode 0 = normal 1 = force ...
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CONFIGURATION REGISTER ADDRESS 36 (48h) R/W SCRAMBLER SEED LONG PREAMBLE Bit 7 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 6:0 Scrambler seed for long preamble bit 3 of CR5 ...
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CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W RF ATTENUATOR VALUE Bit 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 5:0 CR_AGC_rxAGCpad value to use in the RSSI calculation. Range 0-63. ...
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CONFIGURATION REGISTER ADDRESS 59 (78h MEAN POWER Bit 7:0 a&b: Average power of received signal after log table lookup (0-255 range) CONFIGURATION REGISTER ADDRESS 60 (7Ah) R RX_IF_AGC Bit 7 a&b: unused Bits 6:0 a&b: AGC output to ...
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Absolute Maximum Ratings Supply Voltage ...
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AC Electrical Specifications V PARAMETER TX_CLK to TX_PE Inactive (11Mbps) TX_RDY Inactive to Last Chip of MPDU Out TXD Modulation Extension RX_PE Inactive Width RX_CLK Period (11Mbps Mode) RX_CLK Width Hi or Low (11Mbps Mode) RX_CLK to RXD MD_RDY to ...
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I and Q A/D AC Electrical Specifications PARAMETER Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) NOTE: 21. Not tested, but characterized at initial design and at major process/design changes. ...
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Waveforms (Continued) TX_PE OUT OUT TXRDY TX_CLK TXD t RLP RX_PE MD_RDY RX_CLK RXD CCA, RSSI NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. ...
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Thin Plastic Quad Flatpack Packages (TQFP -D- - PIN 1 - -13 0.020 0.008 MIN o 0 MIN A2 A1 GAGE PLANE -13 0. 0.010 0 -7 ...