HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 22
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HFA3861AIN
Manufacturer Part Number
HFA3861AIN
Description
Processor, Direct Sequence Spread Spectrum Base band Processor
Manufacturer
Intersil Corporation
Datasheet
1.HFA3861AIN.pdf
(37 pages)
NOTE:
3. This register is written, then the data is loaded into register 23 as per the following table.
CONFIGURATION
REGISTER
CR40
CR41
CR42
CR43
CR44
CR45
CR46
CR47
CR48
CR49
CR50
CR51
CR52
CR53
CR54
CR55
CR56
CR57
CR58
CR59
CR60
CR61
CR62
CR63
DECIMAL
CR22
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
AGC REGISTER SETTINGS
TABLE 9. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY (Continued)
Threshold for antenna decision
Preamble tracking loop lead coefficient
Preamble tracking loop lag coefficient
Header tracking loop lead coefficient
Header tracking loop lag coefficient
Data tracking loop lead coefficient
Data tracking loop lag coefficient
RF attenuator value
ED and SQ1 control and SQ1 scale factor
Read only register mux control for registers 50 to 63
a&b: Test Bus Read
a: Noise floorAntA
b: Signal Quality Measure Based on Carrier Tracking
a: Noise floorAntB
b: Received Signal Field
a: AGC error
b: Received Service Field
b: Received Length Field, Low
b: Received Length Field, High
b: Calculated CRC on Received Header, Low
b: Calculated CRC on Received Header, High
b: TX Power Measurement
b: RX Mean Power
b: RX_IF AGC
b: RX Status Reg
b: RSSI
b: RX Status Reg
22
CR23
HEX
0C
1C
3C
10
14
18
20
24
28
2E
34
38
3F
43
46
48
NAME
HFA3861A
DECIMAL
AGC REGISTER SETTINGS (Continued)
CR22
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRESS HEX
REGISTER
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
7A
7C
7E
CR23
HEX
5A
6D
1/2/5.5/11Mbps
46
50
55
63
76
7F
7F
7F
7F
7F
7F
7F
7F
7F
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0F
20
1E
1A
20
10
10
10
10
00