SD1010-1199A N/A, SD1010-1199A Datasheet
SD1010-1199A
Related parts for SD1010-1199A
SD1010-1199A Summary of contents
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... OVERVIEW The SD1010A is enhanced version of the SD1000 chip designed for analog-interface XGA TFT LCD monitors. An analog-interface LCD monitor takes analog RGB signals from a graphic card of a personal computer, the exact same input interface as a conventional CRT monitor. This feature makes analog-interface LCD monitor a true replacement of a conventional CRT monitor ...
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... SmartASIC, Inc. Figure 1: SD1010A Functional Block Diagram ADC Input Mode Detection & Auto Calibration Phase Control Input PLL November, 1999 Revision B Buffer Scaling Memory Interpolation Dithering Write Read Control Control CPU 2 E ROM Interface Interface Output CPU E PLL SmartASIC Confidential SD1010A ...
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... SmartASIC, Inc. 2. PIN DESCRIPTION Figure 2: SD1010A package diagram 102 103 SmartASIC SD1010A 128 1 November, 1999 Revision SmartASIC Confidential SD1010A ...
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... SmartASIC, Inc. Table 1: SD1010 pin description (sorted by pin number) Symbol PIN Number ROM_SCL 1 ROM_SDA 2 GND 3 CPU_SCL 4 CPU_SDA 5 PWM_CTL 6 CLK_1M 7 VDD 8 CLK_1M_O 9 RESET_B 10 R_OSD 11 G_OSD 12 B_OSD 13 EN_OSD 14 SCAN_EN 15 TEST_EN 16 FCLK0 17 VCLK0 18 FCLK1 19 VCLK1 20 HSYNC_O 21 VSYNC_O 22 DCLK_OUT 23 DE_OUT 24 GND 25 VDD 26 R_OUT0_E 27 R_OUT1_E 28 R_OUT2_E ...
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... Output Color Blue Odd Pixel (right pixel) O Output Color Blue Odd Pixel (right pixel) O Output Color Blue Odd Pixel (right pixel) Ground I Channel A Data Input Color Red (LSB) I Channel A Data Input Color Red I Channel A Data Input Color Red SmartASIC Confidential SD1010A 7 ...
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... Channel A Data Input Color Blue I Channel A Data Input Color Blue I Channel A Data Input Color Blue I Channel A Data Input Color Blue (MSB) Ground I Input HSYNC (any polarity) I Input VSYNC (any polarity input for digital interface (reserved) Power Supply SmartASIC Confidential SD1010A 8 ...
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... SmartASIC, Inc. Table 2: SD1010 pin description (sorted by function) Symbol PIN Number R_IN00 90 R_IN01 91 R_IN02 92 R_IN03 93 R_IN04 95 R_IN05 96 R_IN06 97 R_IN07 98 G_IN00 102 G_IN01 103 G_IN02 104 G_IN03 105 G_IN04 107 G_IN05 108 G_IN06 110 G_IN07 111 B_IN00 115 B_IN01 116 B_IN02 117 ...
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... CPU, default is active HIGH) O Input PLL Feedback Clock I Input Clock 0 O Output PLL Feedback Clock I Output PLL Output Clock 2 O SCL for EEPROM interface 2 I/O SDA for EEPROM interface 2 I SCL for CPU interface SmartASIC Confidential SD1010A 10 ...
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... Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground SmartASIC Confidential SD1010A 11 ...
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... SmartASIC, Inc. November, 1999 Revision B SmartASIC Confidential SD1010A 12 ...
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... Input mode detection & auto calibration block 3.1.1. Supported input modes SD1010A can handle different input modes. For SD1010A, an input mode is defined by its horizontal resolution with its vertical resolution. The input modes with the same horizontal and vertical resolution but with different frame rates are still considered as one single input mode ...
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... Phase calibration The SD1010A can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of the input signal and to get the best quality. The SD1010A implements a proprietary image quality function. During the auto-calibration process, the SD1010A continues to search for the best phase to optimize the image quality. ...
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... SmartASIC, Inc. The PWM signal from the SD1010A is a periodical signal with a period that is 1023 times the period of the free-running clock connected to the pin “CLK_1M”. System manufacturers may select any frequency for the free running clock. The default clock frequency is 1MHz. System manufacturers also decide the unit delay for the external delay circuit ...
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... Text Enhancement In order to generate a good picture, the SD1010A incorporate a proprietary scheme to detect text and non-text picture. Then applying the appropriate process to improve the text image based on the detection of incoming source. By using the text enhancement ...
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... OSD mixer In the OSD mixer block, the SD1010A mixes the normal output RGB signal with the OSD signal. The OSD output data is generated based on the “R_OSD”, “G_OSD” and “B_OSD” pins as well as the “OSD Intensity” data in EEPROM entry. When the “ ...
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... The 2-wire serial interface uses 2 wires, SCL and SDA. The SCL is driven by the SD1010A and used mainly as the sampling clock. The SDA is a bi-directional signal and used mainly as a data signal. Figure 4 shows the basic bit definitions of the 2-wire serial interface ...
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... SmartASIC, Inc. Figure 4: START, STOP AND DATA Definitions in 2-wire serial interface SDA SCL START DATA CHANGE November, 1999 Revision B DATA STABLE DATA CHANGE SmartASIC Confidential SD1010A STOP 19 ...
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... November, 1999 Revision WORD ADDRESS DEVICE [5:0] ADDRESS R P [6: SmartASIC Confidential SD1010A DATA READ ...
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... EEPROM contents to distinguish their monitors. The EEPROM contents can be partitioned into 15 parts. The first 14 parts are input mode dependent. When the SD1010A detects the input mode, it will then load the information related to the detected mode from the EEPROM. The information in the ...
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... Part 5: mode 5: 800x600 mode (in default setting) Part 6: mode 6: 832x624 mode (in default setting) Part 7: mode 7: 1024x768 mode (in default setting) Part 8: mode 8 Part 9: mode 9 Part 10: mode 10 Part 11: mode 11 Part 12: mode 12 Part 13: mode 13 Part 14: mode 14 Part 15: input mode detection and scaling related parameters November, 1999 Revision B SmartASIC Confidential SD1010A 22 ...
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... When the input has fewer lines than this value considered as an ERROR, and INPUT_X status bit will be HIGH. Maximum input pixels per line. Auto clock recovery will not set input PLL divisor larger than this value. Source horizontal size upper 3 bits Source vertical size upper 3 bits SmartASIC Confidential SD1010A 23 ...
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... Bit 6 – bit 0 : device ID for external CPU access Bit 7: fixed at 1 (reserved) 201H Bit0: 0: disable automatic input gain control 1: enable automatic input gain control Bit1: 0: enable input H/V SYNC polarity control (make input SYNC positive polarity) 1: bypass input H/V SYNC polarity control Bit2: fixed at 0 (reserved) SmartASIC Confidential SD1010A 24 ...
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... Upper bound of the line number for 800x600 mode, and lower bound for 832x624 20DH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 20DH[2:0] Upper bound of the line number for 832x624 mode SmartASIC Confidential SD1010A 25 ...
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... The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 21DH[2:0] Resolution threshold for reserve mode 7 21EH Resolution threshold for reserve mode 7 21FH-220H Enable SYNC polarity check during input mode detection. 1: enable SYNC polarity based mode detection SmartASIC Confidential SD1010A 26 ...
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... If the intended maximum refresh rate is 75Hz, and the free-running clock is 1MHz, then a value of 1000000/75=133,333 is used here 261H Maximum source clock rate supported by the SD1010 (unit: frequency of free-running clock). If the intended maximum clock rate is 60MHz, and the free-running clock is 1MHz, then a value used here ...
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... Enable for programmable output pad: 1: output is enabled 0: output is tri-state 267H[6:4] 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA 267H[3] Enable for programmable output pad: 1: output is enabled 0: output is tri-state 267H[2:0] 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA SmartASIC Confidential SD1010A 28 ...
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... Gamma_scalefactor4 for red 28AH Gamma_scalefactor5 for red 28BH Gamma_scalefactor6 for red 28CH Gamma_scalefactor7 for red 28DH Gamma_scalefactor0 for green 28EH Gamma_scalefactor1 for green 28FH Gamma_scalefactor2 for green 290H Gamma_scalefactor3 for green 291H Gamma_scalefactor4 for green 292H Gamma_scalefactor5 for green SmartASIC Confidential SD1010A 29 ...
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... CPU interface The SD1010A supports a 2-wire serial interface to an external CPU. The interface allows the external CPU to access and modify control registers inside the SD1010A. The 2-wire serial interface is similar to the EEPROM interface, and the CPU is the host that drives the SCL all the time as the clock and for “start” and “stop” bits. The SCL frequency can be as high as 5MHz ...
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... The following table briefly describes the SD1010A control registers. The external CPU can read these registers to know the state of the SD1010A as well as the result of input mode detection and phase calibration. The external CPU can modify these control registers to disable several SD1010A features and force the SD1010A into a particular state ...
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... Disable auto calibration for this mode: 1: disable 0: enable 23H[6:0]- The number of frames need to be skipped before 24H starting auto calibration for this mode 25H[7] Disable auto calibration for this mode: 1: disable 0: enable SmartASIC Confidential SD1010A 32 ...
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... Should be kept low most of the time. A high pulse will force SD1010 to reload mode dependent EEPROM entries 29H[0] External CPU control enable: 0: disable external CPU control. SD1010 can write control registers, but CPU only read control registers. 1: enable external CPU control. CPU can read/write control registers. SD1010 cannot write control ...
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... Comparison Value” and check register “Status 2[1:0]” Bit [4:3]: Brightness Control: 0: disable brightness control(default) 1: reduce brightness 2: increase brightness 3: invalid *Using brightness control should specify register “Brightness Adjustment” and check register “Status 2[2]” SmartASIC Confidential SD1010A after state 10) 34 ...
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... Processing B Value” for properly functioning Bit [6]: Dithering Scheme Selection 0: Scheme A(default) 1: Scheme B Bit [7]: Reserved 2FH[7:0] Control Register D Bit [3:0]: Advanced Processing Shift Amount. From 0 – the default value. Bit [4]: Advance Mixing Shift Enable 0: disable(default) 1: enable SmartASIC Confidential SD1010A Processing G Weight”, 35 ...
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... Comparison Value” 2: incoming pixel = “Pixel Comparison Value” 3: incoming pixel < “Pixel Comparison Value” Bit [2]: Status for brightness control 0: Normal, no underflow/overflow 1: brightness reduced underflow/increased too much causes overflow SmartASIC Confidential SD1010A For Reducing/Increasing too much causes 36 ...
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... Bit[1]: Reserved Bit[6:2]: text-enhanced level Level 0 – 14. Level “0” is the same as original source, and “14” is the highest enhancement level. Bit[7]: Reserved Default is 00H 53H[7:0] Sharpness-Enhancement Control Bit[0]: sharpness enhancement enable 0: disable 1: enable Bit[1]: Reserved SmartASIC Confidential SD1010A 37 ...
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... Bit[7]: Reserved Default is 14H 54H[7:0] Control Register E Bit[3:0]: text enhancement threshold. Bit[4]: reserved Bit[6:5]: Frame Modulation Mode 0: compatible with SD1010 1-3: new schemes Bit[7]: reserved Default is 05H 55H[10:8] The x location for reading “Pixel_out” register 56H[7:0] 57H[10:8] The y location for reading “ ...
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... Rom_clk_sel 6 RW 3.7. Control Flow When SD1010A is powered up, the reference system and SD1010A will perform the following functions in sequence: 1. System will generate a Power-On Reset to SD1010A. 2. Once the SD1010A receives the Reset, SD1010A will load the contents of EEPROM and start the auto-calibration process. ...
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... SmartASIC, Inc the meantime, the external CPU can change the contents of the control registers of the SD1010A. If necessary, the external CPU can send an additional Reset to restart the whole process. November, 1999 Revision B SmartASIC Confidential SD1010A 40 ...
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... SmartASIC, Inc. 4. ELECTRICAL SPECIFICATIONS This section presents the electrical specifications of the SD1010A. 4.1. Absolute Maximum Ratings Symbol Parameter VCC Power Supply Vin Input Voltage Vout Output Voltage VCC5 Power Supply for 5V Vin5 Input Voltage for 5V Vout5 Output Voltage for 5V TSTG Storage Temperature 4 ...
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... IOH=2,4,8,12, 2.4 16,24 mA VIL=0V or VIH=VCC =4.75~5.25,T CC Conditions Min. COMS COMS 0.7*VCC TTL TTL 2.0 CMOS COMS TTL TTL IOL=2,4,8,16,24mA IOH=2,4,8,16,24 3.5 mA VIL=0V or VIH=VCC SmartASIC Confidential SD1010A = +115 C) J Max. Units 0.3*VCC 0 +115 C) J Typ. Max. Units 0.3*VCC ...
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... SmartASIC, Inc. 5. PACKAGE DIMENSIONS 128 1 128 PQFP (14x20 mm November, 1999 Revision SmartASIC Confidential SD1010A 102 ...
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... D 0.551+/-0.002 E 0.787+/-0.002 e 0.020 (Ref) HD 0.677 +/- 0.01 HE 0.913 +/- 0.01 L 0.035+/-0.006 L1 0.063(Ref 7.0 November, 1999 Revision B MM (Base) 3.40 (Max) 0.25 (Min) 2.85 +/- 0.08 0.17(Min) – 0.27(Max) 0.09(Min) – 0.20(Max) 14.000+/-0.10 20.000+/-0.10 0.5 (Ref) 17.20 +/- 0.25 23.20 +/- 0.25 0.88+/-0.15 1.60(Ref 7.0 SmartASIC Confidential SD1010A 44 ...
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... November, 1999 Revision B Package Speed 128-pin PQFP 100MHz (mm) WORLDWIDE OFFICES Asia Pacific 3F, No. 68, Chou-Tze St. Nei-Hu Dist. Taipei 114, Taiwan R.O.C. Tel : 886-2-8797-7889 Fax : 886-2-8797-6829 SmartASIC Confidential SD1010A 45 ...