SD1010-1199A N/A, SD1010-1199A Datasheet - Page 38

• Manufacturer Part Number: SD1010-1199A
• Description: Analog-Interface XGA TFT LCD Display Controller
• Manufacturer: N/A

November, 1999
Revision B
SmartASIC, Inc.
ICS_phase_state
Hsize_by842_en
Channel_select
Video_mode
Yuv_signed
Dual_pixel
decimation
Control_E
Input_yuv
Detect_en
Soft_start
Pixle_out
Fc3_start
Pixel_h
Pixel_v
11
11
24
8
1
1
1
1
1
1
1
1
1
1
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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R
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59H, 5AH,
55H[10:8]
57H[10:8]
5DH[2:1] Input data range detection.
54H[7:0] Control Register E
56H[7:0]
58H[7:0]
5CH[4]
5CH[3]
5CH[2]
5CH[1]
5CH[0]
5DH[7]
5DH[6]
5DH[5]
5DH[4]
5DH[3]
5BH
Bit[6:2]: sharpness-enhanced level
Level 1 – 19. Level “5” is the same as the original
source. From “4” to “1” intend to soften the picture,
and “1” is the softest level. From level “6” to “19” will
sharpen the picture gradually.
sharpest output.
Bit[7]: Reserved
Default is 14H
Bit[3:0]: text enhancement threshold.
Bit[4]: reserved
Bit[6:5]: Frame Modulation Mode
0: compatible with SD1010
1-3: new schemes
Bit[7]: reserved
Default is 05H
The x location for reading “Pixel_out” register
The y location for reading “Pixel_out” register
Read out pixel located by “Pixel_h” and “Pixel_v”
Forces auto calibration to recalculate h back porch
Only for single pixel input
0: takes input data from channel 1
1: takes input data from channel 0
For 128 pin package, set this bit at 0
0: takes input from one single channel
1: takes input from both channels.
For 128 pin package, set this bit at 0
Restarts auto calibration without going into reset
Forces auto calibration to calculate the image quality
for a particular clock phase when supplied by ics chips
Turn on internal hsize matching by8, 4, 2 when clock
frequency calibration is done by8, 4, 2. Used mainly
for special non-full screen inputs.
0: disable input video mode
1: input is video
0: input video format is RGB
1: input video format is YUV 4:2:2
0: input video YUV format is unsigned
1: input video YUV format is signed
Used when input resolution is higher than output
1: enable special decimation control
0: disable special decimation
register 64H and 65H
The results are put in
Level “19” is the
SD1010A
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