SD1010-1199A N/A, SD1010-1199A Datasheet - Page 37

• Manufacturer Part Number: SD1010-1199A
• Description: Analog-Interface XGA TFT LCD Display Controller
• Manufacturer: N/A

November, 1999
Revision B
Image Quality Index
Standalone Enable
SmartASIC, Inc.
Sharpness Control
Recovery Control
Reserved Entry
Waiting Time
PWM Enable
Phase Range
Text Control
Quick Phase
Phase Offset
Phase Track
Phase Total
Enable
24
10
10
30
8
4
1
1
1
1
8
8
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
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4EH[5:0],4
FH, 50H,
52H[7:0] Text-Enhancement Control
53H[7:0] Sharpness-Enhancement Control
49H[0]
49H[1]
49H[2]
49H[3]
4AH
4BH
4CH
4DH
44H
45H
46H
48H
51H
Bit [7:3]: Reserved
Clock Recovery Control Register:
Default value is 71H
Bit 0: clock frequency is divisible by 2
Bit 1: clock frequency is divisible by 4
Bit 2: clock frequency is divisible by 8
Bit 3: enable phase tracking feature
Bit 4: enable auto phase calibration
Bit 5: enable auto frequency calibration
Bit 6: enable auto mode detection
Bit 7: fixed at 0 (reserved)
Offset value added to the calibrated phase when phase
tracking occurs
Number of frames waited before phase tracking occurs
0: Normal phase calibration (default)
1: Final phase = phase total – phase offset
0: Disable auto phase total calculation
1: Enable auto phase total calculation (default)
0: Uses the external incoming SYNC signals
1: Allow the use of the default SYNC signals
Fixed at 0 (reserved)
Offset value subtracted from phase total when doing
quick phase calculation
User defined value for a particular frequency
Read only register for CPU to monitor Image Quality
Index. The Image Quality Index is used by auto phase
calibration.
Bit[0]: text enhancement enable
0: disable
1: enable
Bit[1]: Reserved
Bit[6:2]: text-enhanced level
Level 0 – 14. Level “0” is the same as original source,
and “14” is the highest enhancement level.
Bit[7]: Reserved
Default is 00H
Bit[0]: sharpness enhancement enable
0: disable
1: enable
Bit[1]: Reserved
instead of the incoming SYNC signals
(default)
SD1010A
37