CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 16

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Figure 21: Sync Monitor
Figure 21 conceptually illustrates the Sync Monitor circuitry
used to phase lock 'out-of-sync' states. When both BLK and
SBD signals are high, the Sync Monitor circuitry operates in a
burst mode fashion. This provides a mechanism to flag
BLKERR as well as resetting BLKERR at the end of an output
decoded Viterbi/TCM data stream, on BLKSTOPO. Figure 22
graphically demonstrates both 'in-sync' and 'out-of-sync'
conditions.
Figure 22: Sync Monitor Operation
Figure 23: ‘In Sync’ Burst Dependent Phase Lock Monitoring
16
"Normalisation"
CS3410
BLKSTARTI
BLKSTOPO
120
100
80
60
40
20
DVALI
0
CLK
0
Out-of-sync
200
BLKSTOPO
SYNCUP
BLKERR
OSYNC
SYNCS
400
CLK
High Speed Viterbi/TCM Decoder
Sync Monitor
TPERIOD Count
600
In-sync
800
1000
Thres
OSYNC
SYNCUP
BLKERR
SYNCS
1200
The y-axis describes the accumulated 'Normalization' count
value and the x-axis defines count period for this
measurement (TPERIOD). If THRES signal is set somewhere
between a worst case and best case the 'Normalization' value
at 'time' TPERIOD (which is incremented on DVALI signal)
then an 'out'-of-sync' case be easily discerned. It should be
noted that the value of THRES depends upon noise on the
received data and thus a THRES searching technique should
be employed to establish a phase lock. This would involve the
step-by-step reduction of an initially high THRES value (over
time) until a lock is established and the core correctly decodes
data. Such values are determined experimentally. Figures 23
through 26 show the waveform operation of the Sync Monitor
circuitry. Figure 23 and Figure 24 demonstrate the core
configured to provide phase synchronisation information that
is burst dependent.
This mode of operation is defined as follows: BLK = 1, and
SBD = 1; internal TPERIOD/Normalization count values are
reset on BLKSTARTI; BLKERR is reset on BLKSTOPO. This
mode of operation is useful in cases where input symbol data
arrive from multiple demodulator sources. In this case it is
possible that each demodulator may have established a
separate and independent phase lock. Figure 25 and Figure 26
demonstrate the core configured to provide continuous phase
synchronisation information regardless of BLK (BLK=0/1; SBD
= 0).
In this case BLKERR is never asserted and BLKSTARTI/
BLKSTOPO has no effect on TPERIOD/Normalization values.
Note SBD signal should never be asserted when BLK = 0 as
this will activate the ERR flag of the CORE STATUS register in
the microprocessor interface.