CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 2

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Table 1 provides the descriptions of the input and output
ports of the CS3410 Viterbi/TCM decoder (shown graphically
in Figure 2). Unless otherwise stated, all signals are active
high and bit(0) is the least significant bit.
2
R0
R1
R2
R0ERASE
R1ERASE
R2ERASE
I
Q
CLK
RESET
CHSYNC
BLKSTARTI
BLKSTOPI
DVALI
SYNCS
OSYNC
CS3410
Signal
CS3410 SYMBOL AND
PIN DESCRIPTION
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 1: CS3410 - Viterbi/TCM Decoder Interface Signal Definitions
Width (Bits)
High Speed Viterbi/TCM Decoder
4
4
4
1
1
1
8
8
1
1
1
1
1
1
1
1
Soft decision vector from demodulator (Viterbi mode)
Soft decision vector from demodulator (Viterbi mode)
Soft decision vector from demodulator (Viterbi mode – rate 1/3)
Erase flag (used to obtain external punctured codes in Viterbi mode) – when active,
internal circuitry ignores R0 vector contribution during branch metric calculations.
Erase flag (used to obtain external punctured codes in Viterbi mode) – when active,
internal circuitry ignores R1 vector contribution during branch metric calculations.
Erase flag (used to obtain external punctured codes in Viterbi mode) – when active,
internal circuitry ignores R2 vector contribution during branch metric calculations
(Viterbi mode – rate 1/3)
I vector direct from demodulator (TCM mode)
Q vector direct from demodulator (TCM mode)
Clock
Asynchronous reset
External synchronization control (see ADD8 register) – rising edge sensitive.
Start of block marker – marks the first valid input data symbol
End of block marker – marks the last valid input data symbol
Input data valid
Synchronization status: 0 indicates perfect synchronization; 1 indicates that input
data is rotated and synchronization is required - updated on SYNCUP.
‘Out-of-sync’ as a result of THRES comparison – high if THRES is exceeded during
any test period. This signal indicates a loss of synchronization – updated on SYN-
CUP (valid for one clock cycle).
Figure 2: CS3410 Symbol
R0ERASE
R1ERASE
R2ERASE
RESET
CLK
R0
R1
R2
Q
I
Description
µ
P Interface
OSYNC
SYNCUP
BERDONE
VITDATA
TCMDATA
DVALO
BLKSTARTO
BLKSTOPO
SYNCS
BLKERR
Sync
Status