CS3410 Amphion Semiconductor Ltd., CS3410 Datasheet - Page 9

• Manufacturer Part Number: CS3410
• Description: High Speed Viterbi/TCM Decoder
• Manufacturer: Amphion Semiconductor Ltd.

Figure 12: Encoder Output Mapping for 8-PSK
Figure 13: Encoder Output Mapping for 16-PSK
Viterbi Decoder
BM values are processed using a k = 7, rate = 1/2 Viterbi
decoder to obtain a decoded output bit.
Phase Ambiguity Resolution Decoding (PARD)
The output of the Viterbi decoder is passed into the PARD
pre-processor
estimates the original TCM encoded sequence for the PARD
and re-encodes the decoded bit from the Viterbi decoder core
to generates the best estimate of the transmitted bits,
TCMEnc[0] and TCMEnc[1]. These bits correspond to
1100
0110
1101
0
1
0111
1111
100
DEC
ADDRESS
010
101
shown
0101
1110
7
8
0
1
9
6
4
3
HEX
10
in
5
2
5
11
0100
4
1000
011
111
Figure 11.
12
Bit 7
Bit 15
3
6
1
13
2
D7
7
14
0
1
15
1001
0010
0
Table 4: CS3410 Configuration Registers
The
001
110
Bit 6
Bit 14
0011
1011
000
D6
pre-processor
0001
1010
0000
Bit 5
Bit 13
D5
BPERIOD MS BYTE
BPERIOD LS BYTE
multiple possible phase angles (Figure 12 and Figure 13) in
PSK transmission. In 8-PSK, this corresponds to 2 possible
phases while in 16-PSK this corresponds to 4 possible phases.
The computed sector number for that point is delayed to
arrive with its corresponding decoded bit through the Viterbi.
The trellis mapper is employed to determine the correct phase
angle for that instance, TCMEnc[2] (8-PSK/16-PSK) and
TCMEnc[3] (16-PSK). The pre-processed data is then passed
through a PARD to produce decoded TCM data.
An 'out-of-sync' condition can arise in TCM mode when input
vectors (signed magnitude I/Q) are rotated. In this case two
scenarios are possible:
1.
2.
MICROPROCESSOR INTERFACE
DESCRIPTION
This byte-wide interface allows the configuration of the
CS3410 to be set by a microprocessor. Twelve 8-bit setup/
control registers are accessible through this interface (see
Table 2). Address lines (ADD) select an 8-bit register for a read
(RD) or write (WR) access. Write and read data are supplied
to/from CS3410 on the UP_DIN and UP_DOUT buses
respectively. To write to a register the WR signal must be set
high with the associated address value on the ADD bus. On
the next positive clock edge after WR has been asserted high
the core is configured. The registers may be read by asserting
the RD line high with the address bus ADD being set to the
address of the register to be read.
MICROPROCESSOR CONFIGURATION
REGISTERS
Table 4 provides detailed information on the configuration
registers of the CS3410.
Bit 4
Bit 12
DATA BITS
D4
Sector Number Rotator ('Sector Number Rot') rotates the
sector number by 1 (anti-clock wise)
BM values are rotated. Both these events enable the core
to establish a correct phase lock and successfully decode
data (refer to Phase Synchronization Section).
Bit 3
Bit 11
D3
Bit 2
Bit 10
D2
Bit 1
Bit 9
D1
Bit 0
Bit 8
D0
9
TM