CS61310-CL Cirrus Logic, Inc., CS61310-CL Datasheet
CS61310-CL
Related parts for CS61310-CL
CS61310-CL Summary of contents
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... Final Product Information Cirrus Logic, Inc. http://www.cirrus.com T1 Line Interface Unit Description The CS61310 primary rate line interface unit. It combines the complete analog transmit-and-receive cir- cuitry for a single, full-duplex interface at T1 rates. The device is pin- and function-compatible with the Level One LXT310. ...
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... I C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 CS61310 2 C Patent Rights to use DS440F1 FEB ‘03 ...
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... Figure 14. Matched Impedence Output Configuration ................................................................ 28 LIST OF TABLES Table 1. Pulse Shape Selection and Transformer Requirements ............................................... 9 Table 2. Data Output/Clock Relationship.................................................................................. 10 Table 3. Register Map............................................................................................................... 13 Table 4. Register 16 Decoding ................................................................................................. 15 Table 5. CS61310 Diagnostic Mode Availability ....................................................................... 18 Table 6. Transformer Specification ........................................................................................... 19 Table 7. Recommended Tranformers for the CS61310 ............................................................ 19 DS440F1 FEB ‘03 CS61310 3 ...
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... RV+, TV+ 4.75 T -40 A (Notes Symbol Min (Note 6) V 2.0 IH PINS 1-4, 24-28 (Note PINS 1-4, 24-28 (Notes 2.4 OH PINS 6-8, 25 (Notes PINS 6- 2 OUT CS61310 Min Max Units - 6 (RV+) + 0.3 V (RV+) + 0 °C -40 85 °C -65 150 Typ Max Units 5.0 5.25 V ° ...
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... T1, DSX-1 (Note 10) 2.4 4.8 (Note 12) FCC DSX1 External Equalizer (Notes 11,12 kHz 8 kHz - 40 kHz kHz Broad Band (Notes 8, 12) 12.6 (Notes 8, 12) -29 (Notes 8, 12) (Notes 8, 13) -40 30 T1, DSX-1 T1, (FCC Part 68) 160 0.4 (Note 12 138 CS61310 Typ Max 3.0 3.3 3.0 3.6 5.6 1 0.015 - - 0.015 - - 0.015 - - 0.020 - 15 17.9 -38 ...
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... CS61310 Typ Max Units 1.544 - MHz 1.544 - MHz 274 - ns 274 - ns 274 ...
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... Figure 3. Transmit Clock and Data Switching Characteristics DS440F1 FEB ‘ 90% 10% Figure 1. Signal Rise and Fall Characteristics su2 CS61310 t f 90% 10 ...
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... Figure 4. Serial Port Write Timing Diagram Figure 5. Serial Port Read Timing Diagram CS61310 Min Typ Max 240 - - 240 - - - - ...
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... THEORY OF OPERATION The CS61310 Line Interface Unit is a fully integrat- ed transceiver for T1 long haul applications. The transmitter outputs all pulse shapes for T1 applica- tions. 2.1 Interface Modes The CS61310 can be operated as a stand-alone device with its interface in hardware mode (MODE pin is low can be operated by a microcontrol- ler over a serial interface in host mode (MODE pin is high) ...
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... Clock Recovery The clock recovery circuit is a third-order phase- locked loop. The digital PLL in the clock recovery circuit of the CS61310 recovers clock from the edges of the incoming pulses (1’s). The clock and data recovery circuit is tolerant of long strings of consecutive zeros, and will successfully receive a 1-in-175, jitter-free input signal ...
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... XTALIN pin high. The jitter attenuator on the CS61310 does not require a crystal ac- tivated when XTALIN is either connected to ground or left open; connecting to ground is the preferred method. ...
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... SDO goes high-impedance after CS goes high or at the end of the hold period of data bit D7. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applica- tions where the host processor has a bi-directional I/O port. CS61310 DS440F1 FEB ‘03 ...
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... LLOOP RLOOP LB02 RSVD RAMPLSE LOOPDN LOOPUP set to “0” EQ4 - - - Table 3. Register Map CS61310 Input/O utp CODER LB01 NLOOP LOS TAZ ...
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... Setting LOOPDN to “1” causes the data pattern 001... to be repetitively transmitted LBO2 LBO1 Attenuation 0 dB -7.5 dB -15 dB -22 RSVD LOOPDN LOOPUP 2 1 CODER NLOOP TAZ RPWDN TxHIZ DS440F1 FEB ‘03 CS61310 0 (LSB) LOS 0 (LSB) RSVD set to “0” ...
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... TAOS active NLOOP has changed state since last TAOS and LLOOP active LOS and NLOOP have both changed CS61310 2 1 EQ2 EQ1 2 1 RAM.2 RAM.1 Status LOS occurred Clear NLOOP occurred state since last Clear NLOOP and Clear LOS Table 4 ...
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... In Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. The re- set will set all registers to “0” and initiate a calibra- tion. In Hardware Mode, the CS61310 is reset by simul- taneously setting RLOOP and LLOOP high for at least 200 ns. Hardware reset will clear Network Loopback functionality 2 ...
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... UI1/phase1, UI1/phase2, ... UI2/phase1, ... , UI2/phase14, UI3/phase1, ... , UI3/phase14. For DSX-1 and DS1 applications, the CS61310 di- vides the 648 ns UI into 13 uniform phases (49.8 ns each), and will ignore the phase amplitude infor- mation written for phase 14 of each UI. When transmitting pulses, the CS61310 will add ...
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... LSB first. The contents of the Arbitrary Waveform register can be verified by reading the Waveform Register. Availability (Note 1) H/W Yes Yes Yes Yes No Yes Yes No Yes Table 5. CS61310 Diagnostic Mode Availability CS61310 Host Mode (Note 2) Host Maskable Yes No Yes No Yes Yes Yes No Yes ...
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... Pulse Engineering Pulse Engineering Valor 1:1CT Pulse Engineering 1:1.5CT Pulse Engineering Table 7. Recommended Tranformers for the CS61310 DS440F1 FEB ‘03 1:1.5, 1:2 step-up transmit, 1:1 receive 1.2 mH min at 772 kHz 0.5 µH max at 772 kHz with secondary shorted 0.5 µH max at 772 kHz 40 pF max, primary to secondary 16 V-µ ...
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... XTALIN XTALOUT JASEL LOS TTIP TGND top 8 view CS61310 TAOS/CLKE LLOOP/SCLK RLOOP/CS LBO2/SDO LBO1/SDI NLOOP/INT RGND RV+ RRING RTIP LATN NC TRING TV+ TAOS/CLKE LLOOP/SCLK RLOOP/CS LBO2/SDO 25 LBO1/SDI 24 NLOOP/INT 23 22 RGND 21 RV ...
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... MCLK is not used, it must be grounded. MODE - Mode Select Input, Pin 5. Setting the MODE pin high puts the CS61310 into Host Mode where the device is controlled by a microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode control where various control and status are provided on dedicated pins ...
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... RCLK. NLOOP - Network Loopback Output, Pin 23 (Hardware Mode). NLOOP goes high when a 00001 pattern is received for five seconds putting the CS61310 into network (remote) loopback. Network loopback is deactivated upon receipt of a 001 pattern for five seconds the selection of RLOOP. Network loopback is temporarily suspended with LLOOP, but the state of the NLOOP pin does not change ...
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... TTIP and TRING. An input on TPOS results in transmission of a positive pulse; an input on TNEG results in transmission of a negative pulse. If TNEG, pin 4, is held high for 16 TCLK cycles, the CS61310 reconfigures for unipolar (single pin NRZ) data input at pin 3, TDATA. If TNEG goes low the CS61310 switches back to two-pin bipolar data input format. ...
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... RPOS, RNEG, and RCLK. TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13,16 These pins are the output of the differential transmit driver. The transformer and matching resistors can be chosen to give the desired pulse height (see Application Schematics) 24 CS61310 DS440F1 FEB ‘03 ...
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... SEATING PLANE BOTTOM VIEW INCHES MIN MAX 0.155 0.200 0.020 0.040 0.014 0.022 0.040 0.065 0.008 0.015 1.435 1.465 0.540 0.560 0.095 0.105 0.600 0.625 0.125 0.150 0° 15° CS61310 ∝ SIDE VIEW MILLIMETERS MIN MAX 3.94 5.08 0.51 1.02 0.36 0.56 1.02 1.65 0.20 0.38 36.45 36.83 13.72 14.22 2.41 2.67 15.24 15.87 3.18 3.81 0° 15° 25 ...
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... JEDEC #: MS-018 CS61310 e D2/ MILLIMETERS MIN MAX 4.572 3.048 0.533 12.573 11.582 10.922 12.573 11.582 10.922 1.524 DS440F1 FEB ‘03 ...
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... CS61310 HARDWARE MODE RGND TGND 22 14 Figure 13. Hardware Mode Operation CS61310 100 Ω (Ω (Ω) 9.1 R3 (Ω) 9.1 R4 (Ω) Lin tting .47 µ ...
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... CS61310 HOST MODE TTIP CS61310 T1 100 Ω (Ω (Ω) µ ria 0.47 µ 0.47 µ ...
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Notes • ...
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