CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet
CS61310-IP
Related parts for CS61310-IP
CS61310-IP Summary of contents
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... LXT310. Enhanced functionality is available through an extended register set allowing custom pulse shape generation and generation and detection of loop up and loop down codes. The CS61310 features Crystal attenuation. ORDERING INFORMATION CS61310-IL CS61310-IP PULSE TRANSMIT SHAPING TIMING & CIRCUITRY CONTROL ROM / RAM TAOS Enable LBO Select REGISTERS & ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS61310 DS440PP2 ...
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... Figure 14. Matched Impedence Output Configuration ................................................... 27 Figure 15. Typical System Connection .......................................................................... 28 LIST OF TABLES Table 1. Pulse Shape Selection and Transformer Requirements ...................................... 8 Table 2. Data Output/Clock Relationship ........................................................................... 9 Table 3. Register Map...................................................................................................... 12 Table 4. Register 16 Decoding......................................................................................... 15 Table 5. CS61310 Diagnostic Mode Availability .............................................................. 17 Table 6. Transformer Specification .................................................................................. 18 Table 7. Recommended Tranformers for the CS61310 ................................................... 18 DS440PP2 CS61310 3 ...
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... P C ( TV+, RV+ = 5.0 V 5%; GND = 0 V) Symbol Min (Note 6) V 2.0 IH PINS 1-4, 24-28 (Note PINS 1-4, 24-28 (Notes 2.4 OH PINS 6-8, 25 (Notes PINS 6- 2 OUT CS61310 Min Max Units - 6 (RV+) + 0.3 V (RV+) + 0 -65 150 C Typ Max Units 5.0 5.25 ...
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... External Equalizer (Notes 11,12 kHz 8 kHz - 40 kHz kHz Broad Band (Notes 8, 12) 12.6 (Notes 8, 12) -29 (Notes 8, 12) (Notes 8, 13) -40 30 T1, DSX-1 T1, (FCC Part 68) 160 0.4 (Note 12 138 resistor across the secondary of the transmitter transformer CS61310 Typ Max 3.0 3.3 3.0 3.6 5.6 6.4 1 0.015 - - 0.015 - - 0.015 ...
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... TCLK t su2 t h2 TPOS/TNEG t r 90% 10% Figure 1. Signal Rise and Fall Characteristics CS61310 Min Typ Max - 1.544 tclk / pw2 - 1.544 / pw1 ...
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... LSB BYTE DATA Figure 4. Serial Port Write Timing Diagram t cdv cdv Figure 5. Serial Port Read Timing Diagram CS61310 ( TV+, RV 5%; Min Typ Max 240 - - 240 - - - - ...
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... Serial Interface section. 2.2 Master Clocks The CS61310 requires a reference clock for the re- ceiver and the jitter attenuator. A 1.544 MHz exter- nal clock can be input to MCLK crystal can be connected to the on-chip oscillator. This fre- quency reference should be within +32 ppm of the nominal operating frequency ...
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... MODE pin can be tied to RCLK enabling the B8ZS encoders and de- coders. The CS61310 will detect the absence of TCLK, and will force TTIP and TRING to high impedance af- ter 175 bit periods, preventing transmission when data input is not present. In host mode, the trans- mitter can be set to high impedance by setting the TxHIZ bit (CR2.1) to “ ...
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... XTALIN pin high. The jitter attenuator on the CS61310 does not require a crystal ac- tivated when XTALIN is either connected to ground or left open; connecting to ground is the preferred method. ...
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... Since the selec- tion is made between a limited set of phases, the Digital Timing Recovery process has a small phase error built into the sampling process. By choosing from 48 possible sampling phases, the CS61310 re- duces the sampling error to a minimum. 2.8 Local Loopback In hardware mode, local loopback is selected by setting the LLOOP pin high (CR1 ...
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... LLOOP RLOOP LB02 RSVD RAMPLSE LOOPDN LOOPUP set to “0” EQ4 - - - Table 3. Register Map CS61310 CODER LB01 NLOOP LOS TAZ RSVD RPWDN TxHIZ set to “0” EQ3 EQ2 EQ1 EQ0 - - - LSB ...
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... LOS = 1 when the loss of signal criteria have been met (175 zeros). LOS = 0 when a valid signal is being received. An interrupt will occur when LOS changes state unless a “1” is written to LOS disabling the in- terrupt. DS440PP2 LB02 LB01 Attenuation 0 dB -7.5 dB -15 dB -22.5 dB CS61310 (LSB) CODER NLOOP LOS TAZ 13 ...
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... The RAM address pointer for the arbitrary waveform memory; a special write procedure must be followed to write the waveform RAM LOOPDN LOOPUP EQ4 EQ3 RAM.4 RAM.3 CS61310 (LSB) RSVD RPWDN TxHIZ set to “0” (LSB) EQ2 EQ1 EQ0 (LSB) RAM.2 RAM.1 RAM ...
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... Network Loopback function. In Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. The re- set will set all registers to “0” and initiate a calibra- tion. In Hardware Mode, the CS61310 is reset by simul- taneously setting RLOOP and LLOOP high for at CS61310 15 ...
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... Figure 11. Phase Definition of Arbitrary Waveforms UI1/phase1, UI1/phase2, ... , UI1/phase14, UI2/phase1, ... , UI2/phase14, UI3/phase1, ... , UI3/phase14. For DSX-1 and DS1 applications, the CS61310 di- vides the 648 ns UI into 13 uniform phases (49.8 ns each), and will ignore the phase amplitude informa- tion written for phase 14 of each UI. ...
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... LSB first. The contents of the Arbitrary Waveform register can be verified by reading the Waveform Register. Availability (Note 1) H/W Yes Yes Yes Yes No Yes Yes No Yes Table 5. CS61310 Diagnostic Mode Availability CS61310 Host Mode (Note 2) Host Maskable Yes No Yes No Yes Yes Yes No Yes ...
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... Valor Pulse Engineering Pulse Engineering Valor 1:1CT Pulse Engineering 1:1.5CT Pulse Engineering Table 7. Recommended Tranformers for the CS61310 18 1:2 step-up transmit, 1:1 receive 1.2 mH min at 772 kHz 0.5 H max at 772 kHz with secondary shorted 0.5 H max at 772 kHz 40 pF max, primary to secondary min Table 6. Transformer Specification ...
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... RCLK XTALIN XTALOUT JASEL LOS TTIP TGND top 8 view CS61310 TAOS/CLKE LLOOP/SCLK RLOOP/CS LBO2/SDO LBO1/SDI NLOOP/INT RGND RV+ RRING RTIP LATN NC TRING TV+ TAOS/CLKE LLOOP/SCLK RLOOP/CS LBO2/SDO 25 LBO1/SDI 24 NLOOP/INT 23 22 RGND 21 RV ...
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... MCLK is not used, it must be grounded. MODE - Mode Select Input, Pin 5. Setting the MODE pin high puts the CS61310 into Host Mode where the device is controlled by a microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode control where various control and status are provided on dedicated pins ...
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... RCLK. NLOOP - Network Loopback Output, Pin 23 (Hardware Mode). NLOOP goes high when a 00001 pattern is received for five seconds putting the CS61310 into network (remote) loopback. Network loopback is deactivated upon receipt of a 001 pattern for five seconds the selection of RLOOP. Network loopback is temporarily suspended with LLOOP, but the state of the NLOOP pin does not change ...
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... TTIP and TRING. An input on TPOS results in transmission of a positive pulse; an input on TNEG results in transmission of a negative pulse. If TNEG, pin 4, is held high for 16 TCLK cycles, the CS61310 reconfigures for unipolar (single pin NRZ) data input at pin 3, TDATA. If TNEG goes low the CS61310 switches back to two-pin bipolar data input format. ...
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... RPOS, RNEG, and RCLK. TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13,16 These pins are the output of the differential transmit driver. The transformer and matching resistors can be chosen to give the desired pulse height (see Application Schematics) DS440PP2 CS61310 23 ...
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... SEATING PLANE BOTTOM VIEW INCHES MIN MAX 0.155 0.200 0.020 0.040 0.014 0.022 0.040 0.065 0.008 0.015 1.435 1.465 0.540 0.560 0.095 0.105 0.600 0.625 0.125 0.150 0° 15° CS61310 SIDE VIEW MILLIMETERS MIN MAX 3.94 5.08 0.51 1.02 0.36 0.56 1.02 1.65 0.20 0.38 36.45 36.83 13.72 14.22 2.41 2.67 15.24 15.87 3.18 3.81 0° 15° DS440PP2 ...
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... JEDEC #: MS-018 CS61310 e D2/ MILLIMETERS MIN MAX 4.572 3.048 0.533 12.573 11.582 10.922 12.573 11.582 10.922 1.524 25 ...
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... TGND 21 15 RV+ TV+ 24 LBO2 25 LBO1 19 CS61310 RTIP IN HARDWARE MODE 20 RRING 16 TRING 13 TTIP RGND TGND 22 14 Figure 13. Hardware Mode Operation 100 9 9 CS61310 Line Length Setting RECEIVE LINE 1CT:1 PE-64936 R3 0. TRANSMIT LINE 6 5 1:2 R4 PE-65351 DS440PP2 ...
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... Figure 14. Matched Impedence Output Configuration DS440PP2 +5V + 0.1 F 1.0 F TGND 21 15 RV+ TV+ 27 SCLK INT 24 SDI 25 SDO CS61310 19 IN RTIP HOST MODE 20 RRING 16 TRING 13 TTIP RGND TGND 100 CS61310 P Serial Port RECEIVE LINE 1CT:1 PE-64936 0. TRANSMIT 6 5 LINE 1:1.5 T-1054 27 ...
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... RLOS 10 sync Data Link Supervision Figure 15. Typical System Connection +5V TV+ TTIP 40 RV+ TRING 19 MODE TCLK 3 TPOS 12 TNEG 13 RCLK 24 RPOS 34 RNEG 35 CLKE INT INT SCLK 18 SDI RTIP 15 SDO RRING Host Processor CS61310 Transmit Line Receive Line DS440PP2 ...
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Notes • ...
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