CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 11

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

data on RPOS/RNEG (RDATA in unipolar mode)
equals 0 (squelched). The device complies with
ANSI T1.231-1993 criteria to exit the LOS condi-
tion: 12.5% ones density for 175+/-75 bit periods
with no more than 100 consecutive zeros.
While LOS is active, RCLK depends on MCLK
and the jitter attenuator. If the jitter attenuator is in
the transmit path or not used, RCLK is referenced
to MCLK, if provided, or the crystal oscillator oth-
erwise. If the jitter attenuator is in the receive path,
the jitter attenuator will hold the average incoming
data frequency prior to LOS. The recovered clock
remains at a 50% duty cycle. The RPOS (RDATA)
and RNEG pins are forced low during LOS.
Timing is recovered by a phase selector which se-
lects one of the phases from the internal synchroni-
zation clock (one of three clocks, 120 degrees apart
in phase, at 16X of the data rate). Since the selec-
tion is made between a limited set of phases, the
Digital Timing Recovery process has a small phase
error built into the sampling process. By choosing
from 48 possible sampling phases, the CS61310 re-
duces the sampling error to a minimum.
2.8
In hardware mode, local loopback is selected by
setting the LLOOP pin high (CR1.6 = 1 in host
mode). Selecting local loopback causes clock and
data presented on TCLK, TPOS/TNEG (TDATA)
to be output at RCLK, RPOS/RNEG (RDATA).
Local loopback disconnects the RTIP/RRING in-
puts from the line. Inputs to the transmitter are still
transmitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-encoded contin-
uous ones are transmitted at the TCLK frequency.
The receiver RTIP and RRING inputs are ignored
when local loopback is in effect.
2.9
Remote loopback is selected by setting the RLOOP
pin high in hardware mode (CR1.5 = 1 in host
mode). In remote loopback, the recovered clock
DS440PP2
Local Loopback
Remote Loopback
and data input on RTIP and RRING are sent back
out on the line via TTIP and TRING. Selecting re-
mote loopback overrides a TAOS request. The re-
covered clock is also sent to RCLK, and the recovered
data is also sent to RPOS and RNEG in bipolar mode,
or RDATA in unipolar mode. Simultaneous selection
of local and remote loopback modes will cause a de-
vice reset to occur (see Reset).
2.10 Network Loopback
Network Loopback (automatic remote loopback)
can be commanded from the network when the
Network Loopback detect function is enabled. In
Host Mode, Network Loopback (NLOOP) detec-
tion is enabled by writing ones to TAOS, LLOOP,
and RLOOP, then clearing these three bits on a suc-
cessive write cycle. In hardware mode, Network
Loopback can be enabled by tying RLOOP to
RCLK or by setting TAOS, LLOOP, and RLOOP
high for at least 200 ns, and then low. Once enabled
Network Loopback functionality will remain in ef-
fect until RLOOP is activated or the device is reset.
When NLOOP detection is enabled, the receiver
monitors the input data stream for the NLOOP data
patterns (00001 = enable, 001 = disable). When an
NLOOP enable data pattern is repeated for a mini-
mum of five seconds (with less than 10E-3 BER),
the device initiates a remote loopback. Once Net-
work Loopback detection is enabled and activated
by the NLOOP data pattern, the loopback is identi-
cal to Remote Loopback initiated at the device.
NLOOP is reset if the disable pattern (001) is re-
ceived for 5 seconds, or by activation of RLOOP.
NLOOP is temporarily suspended by LLOOP, but
the NLOOP state is not reset.
2.11 Alarm Indication Signal
The receiver sets the register bit, AIS, to “1” when
less than 9 zeros are detected out of 8192 bit peri-
ods. AIS returns to “0” upon the first read after the
AIS condition is removed, determined by 9 or more
zeros out of 8192 bit periods.
CS61310
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