CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 15

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

2.13 Interrupts
An interrupt will occur (INT pulls low) in response
to a change in the LOS, AIS or NLOOP bits. The
interrupt is cleared when the host processor writes
a “1” to the respective bit in the control register.
Writing a “1” to LOS or NLOOP over the serial in-
terface has three effects:
1)
2)
3)
Writing a “0” to either LOS or NLOOP enables the
corresponding interrupt for LOS and NLOOP.
Reading the registers returns their current status or
setting. Register 16 outputs the status NLOOP and
LOS and has bits 5, 6, and 7 encoded as shown in
Table 4.
Writing the arbitrary waveform RAM requires a
deviation from normal serial port access. Register
19 is the RAM address register for the arbitrary
DS440PP2
7
0
0
0
0
1
1
1
1
Bits
6
0
0
1
1
0
0
1
1
The current interrupt on the serial interface
will be cleared. (Note that simply reading the
register bits will not clear the interrupt).
Output data bits 5, 6 and 7 will be reset as ap-
propriate.
Interrupts for the corresponding LOS and
NLOOP will be prevented from occurring.
5
0 Reset has occurred, or no program input
1 RLOOP active
0 LLOOP active
1 LOS has changed state since last Clear
0 TAOS active
1 NLOOP has changed state since last
0 TAOS and LLOOP active
1 LOS and NLOOP have both changed
LOS occurred
Clear NLOOP occurred
state since last Clear NLOOP and Clear
LOS
Table 4. Register 16 Decoding
Status
waveform. Two consecutive address bytes are writ-
ten; first the Address/Command Byte is written to
address 0x13, followed by the address in RAM to
be written. This dual address is then followed by
the data byte for the waveform amplitude. There
are 42 RAM byte locations (numbered h00 to h29).
2.14 Power On Reset / Reset
Upon power-up, the IC is held in a static state until
the supply crosses a threshold of approximately
3 Volts. When this threshold is crossed, the device
will delay for about 10 ms to allow the power sup-
ply to reach operating voltage. After this delay, cal-
ibration of the transmit and receive sections
commences. Because power up conditions can vary
considerably, it is recommended that the device be
reset after the power supply has stabilized to ensure
a known initial operational condition.
The internal frequency generators can be calibrated
only if a reference clock is present. The reference
clock for the transmitter is provided by TCLK. The
reference for the receiver is either the crystal oscil-
lator or MCLK. If both the oscillator and MCLK
are active, MCLK will be used as the reference
source. The initial calibration should take less than
20 ms after pulses are input to the receiver.
In operation, the device is continuously calibrated,
making the performance of the device independent
of power supply or temperature variations. The
continuous calibration function forgoes any re-
quirement to reset the line interface when in opera-
tion. However, a reset function is available which
will reinitiate calibration and clear all registers and
clear the Network Loopback function.
In Host Mode, a reset is initiated by simultaneously
writing RLOOP and LLOOP to the register. The re-
set will set all registers to “0” and initiate a calibra-
tion.
In Hardware Mode, the CS61310 is reset by simul-
taneously setting RLOOP and LLOOP high for at
CS61310
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