CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 20

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

4.1
TGND - Ground Transmit Driver, Pin 14.
TV+ - Power Supply, Transmit Driver, Pin 15.
RV+ - Power Supply, Pin 21.
RGND - Ground, Pin 22.
4.2
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
4.3
MCLK - Master Clock Input, Pin 1.
MODE - Mode Select Input, Pin 5.
JASEL - Jitter Attenuator Select, Pin 11.
NC - No Connect, Pin 17.
20
Power Supplies
Oscillator
Control
Power supply ground for the transmit driver; typically 0 Volts.
Power supply for the transmit driver; typically +5 Volts.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
A 6.176 MHz (or 8.192 MHz) crystal can be connected across these pins. This oscillator provides the
reference frequency for the LIU if MCLK is not provided. The load capacitance presented to the crystal
by these pins should be approximately 19pF (IC and package, when soldered into a circuit board). The
jitter attenuator may be disabled by tying XTALIN to RV+ through a 1k
When pin 9 has no clock input, a clock must be supplied to the MCLK pin. Alternatively an external
6.176 MHz (8.192 MHz) clock can be driven into XTALIN, and the jitter attenuator circuit will operate.
If MCLK is provided, and XTALIN is tied low or left floating, the jitter attenuator will be enabled.
Either MCLK or the crystal oscillator provide the master frequency reference for the CS61310. If both
MCLK and the crystal oscillator are present, the oscillator is ignored. MCLK should be 1.544 MHz. If
MCLK is not used, it must be grounded.
Setting the MODE pin high puts the CS61310 into Host Mode where the device is controlled by a
microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode
control where various control and status are provided on dedicated pins. The MODE pin is internally
pulled down placing the part in Hardware Mode when this pin is left floating. Tying the MODE pin to
RCLK places the chip in Hardware Mode and enables the B8ZS encoder/decoder (provided that coder
mode has been enabled; see the description for TNEG/UBS pin).
If the jitter attenuator is enabled (crystal oscillator active, or XTALIN tied low or left floating with MCLK
provided), setting JASEL high places the jitter attenuator in the receive path; setting JASEL low places
the jitter attenuator in the transmit path.
The input voltage to this pin does not effect normal operation.
resistor, and floating XTALOUT.
CS61310
DS440PP2