CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 16

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

least 200 ns. Hardware reset will clear Network
Loopback functionality
2.15 Power Supply
The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies pro-
vide internal isolation. These pins should decou-
pled to their respective grounds.
Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog cir-
cuits in both the transmit and receive paths. A 47 F
tantalum and 1.0 F mylar or ceramic capacitor
should be connected between TV+ and TGND, and
a 0.1 F mylar or ceramic capacitor should be con-
nected between RV+ and RGND. Place capacitors
as closely as possible to their respective power sup-
ply pins. Wire-wrap breadboarding of the line in-
terface is not recommended because lead resistance
and inductance serve to defeat the function of the
decoupling capacitors.
3 ARBITRARY WAVEFORM
In addition to the predefined pulse shapes, the user
can create custom pulse shapes using the host
mode. This flexibility allows the board designer to
accommodate non-standard cables, EMI filters,
protection circuitry, etc.
The arbitrary pulse shape of mark (a transmitted
“1”) is specified by describing it's pulse shape
across three Unit Intervals (UIs). This allows, for
example, the long haul return-to-zero tail to extend
into the next UI, or two UIs, as is required for iso-
lated pulses.
Each UI is divided into multiple phases, and the us-
ers defines the amplitude of each phase. The wave-
form of a space (a transmitted “0”) is fixed at zero
volts. Examples of the phases are shown in
Figure 11. In all cases, to define an arbitrary wave-
form, the user writes to the Waveform Register ei-
ther 36, 39 or 42 times (12, 13 or 14 phases per UI
for three UIs). The phases are written in the order:
16
GENERATION
UI1/phase1, UI1/phase2, ... , UI1/phase14,
UI2/phase1, ... , UI2/phase14, UI3/phase1, ... ,
UI3/phase14.
For DSX-1 and DS1 applications, the CS61310 di-
vides the 648 ns UI into 13 uniform phases (49.8 ns
each), and will ignore the phase amplitude informa-
tion written for phase 14 of each UI.
When transmitting pulses, the CS61310 will add
the amplitude information from the prior two sym-
bols with the amplitude of the first UI of the current
symbol before outputting a signal on TTIP/TRING.
Therefore, a mark preceded by two spaces will be
output exactly as the mark is programmed. Howev-
er, when one mark is preceded by marks, the first
portion of the last mark may be modified. With
AMI data, where successive pulses have opposite
polarity, the undershoot tail of one pulse will cause
the rising edge of the next mark to rise more quick-
ly, as shown in Figure 12.
The amplitude of each phase is described by a 7-bit,
2's complement number, where a positive value de-
scribes pulse amplitude, and a negative value de-
scribes pulse undershoot. The positive full value is
hex 3F. The negative full value is hex 40. For T1,
the typical output voltage is 38 mV/LSB (peak
voltage across the TTIP and TRING outputs).
Figure 11. Phase Definition of Arbitrary Waveforms
DSX-1 (54% duty cycle) Arbitrary Waveform Example
DS-1 (50% duty cycle) Arbitrary Waveform Example
CS61310
DS440PP2