CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 12

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

2.12 Serial Interface
In the Host Mode, pins 24 through 28 serve as a mi-
crocontroller interface. On-chip registers can be
written to via the SDI pin or read from via the SDO
pin at the clock rate determined by SCLK. Through
these registers, a host controller can be used to con-
trol operational characteristics and monitor device
status. The serial port read/write timing is indepen-
dent of the system transmit and receive timing.
Data transfers are initiated by taking the chip select
input, CS, low (CS must initially be high). Address
and input data bits are clocked in on the rising edge
of SCLK. The clock edge on which output data is
stable and valid is determined by CLKE as shown
in Table 2. Data transfers are terminated by setting
CS high. CS may go high no sooner than 50 ns after
the rising edge of the SCLK cycle corresponding to
the last write bit. For a serial data read, CS may go
high any time to terminate the output and set SDO
to high impedance.
12
SDO
CLKE = 0
CS
SCLK
SDI
Control Register 1
Control Register 2
Equalizer Gain
RAM Address
Reserved
(EQGAIN)
Set to “0”
R/W
(RAM)
(CR1)
(CR2)
0
TAOS
Figure 10. Input/Output Timing (showing address 0x10)
Address/Command Byte
MSB
AIS
7
X
0
0
RAMPLSE
LLOOP
0
X
6
0
-
0
Table 3. Register Map
set to “0”
RLOOP
RSVD
1
5
X
0
-
0
LOOPDN
LB02
EQ4
4
Figure 10 shows the timing relationships for data
transfers when CLKE = 0. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th clock
cycle. When CLKE = 0, data bit D7 is held valid
until the rising edge of the 17th clock cycle. SDO
goes high-impedance after CS goes high or at the
end of the hold period of data bit D7.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in applica-
tions where the host processor has a bi-directional
I/O port.
An address/command byte, shown in Figure 10,
points to addresses 0x10 through 0x15 (address
0x10 shown), and precedes a data byte. The first bit
of the address/command byte determines whether a
read or a write is requested. The next six bits con-
tain the address. The last bit is ignored. Data to the
internal registers is input on the eight clock cycles
immediately following the address/command byte.
0
-
0
D0
D0
LOOPUP
LB01
EQ3
3
0
-
D1
D1
D2
D2
RPWDN
CODER
Data Input/Output
EQ2
TAZ
2
0
-
D3
D3
NLOOP
TxHIZ
D4
D4
EQ1
1
0
-
D5
D5
set to “0”
RSVD
LOS
EQ0
LSB
0
0
D6
D6
CS61310
D7
D7
0x10 R/W
0x11 R/W
0x12 R
0x14
0x13 R/W
DS440PP2
ADDR