CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 23

• Manufacturer Part Number: CS61310-IP
• Description: T1 line interface unit
• Manufacturer: Cirrus Logic, Inc.

RRDATA - Received Data, Pin 7.
RCLK - Recovered Clock Output, Pin 8.
RTIP,RRING - Receive Tip, Receive Ring, Pins 19,20.
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13,16
DS440PP2
Unipolar data (single-line NRZ) data is output on RDATA when pin 4, TNEG/UBS, is held high.
RCLK outputs the clock recovered from the input signal at RTIP and RRING. In a Loss of Signal state
RCLK is driven either by MCLK or the crystal oscillator, or retains the frequency prior to the LOS state,
depending on the clocks provided. While LOS is true, RCLK will be driven either by MCLK or the crystal
oscillator. If the jitter attenuator is in the receive path, RCLK will make a smooth transition to the LOS
timing. RCLK will remain at its frequency prior to LOS.
The B8ZS signal received from the line is input via these pins. A 1:1 transformer and appropriate
matching resistors are required as shown in the applications section. Data and clock recovered from the
signal input on these pins is output via RPOS, RNEG, and RCLK.
These pins are the output of the differential transmit driver. The transformer and matching resistors can
be chosen to give the desired pulse height (see Application Schematics)
CS61310
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