CS61310-CL Cirrus Logic, Inc., CS61310-CL Datasheet - Page 13

• Manufacturer Part Number: CS61310-CL
• Description: Interface, T1 Line Interface Unit
• Manufacturer: Cirrus Logic, Inc.

An address/command byte, shown in Figure 10,
points to addresses 0x10 through 0x15 (address
0x10 shown), and precedes a data byte. The first
bit of the address/command byte determines
whether a read or a write is requested. The next six
DS440F1 FEB ‘03
S D O
C L K E = 0
C S
S C L K
S D I
Control Register 1
Control Register 2
Equalizer Gain
RAM Address
Reserved
(EQGAIN)
Set to “0”
R /W
(RAM)
(CR1)
(CR2)
0
Figure 10. Input/Output Timing (showing address 0x10)
TAOS
A ddre ss/C o m m a nd Byte
MSB
AIS
7
X
0
0
RAMPLSE
LLOOP
0
6
X
0
-
0
Table 3. Register Map
set to “0”
RLOOP
RSVD
1
5
X
0
-
0
LOOPDN
LB02
EQ4
4
0
bits contain the address. The last bit is ignored.
Data to the internal registers is input on the eight
clock cycles immediately following the ad-
dress/command byte.
-
0
D 0
D 0
LOOPUP
LB01
EQ3
3
0
-
D 1
D 1
D 2
D 2
RPWDN
CODER
D a ta Input/O utp ut
EQ2
TAZ
2
0
-
D 3
D 3
NLOOP
TxHIZ
D 4
D 4
EQ1
1
0
-
D 5
D 5
set to “0”
RSVD
LOS
EQ0
LSB
0
0
D 6
D 6
CS61310
D 7
D 7
0x10 R/W
0x11 R/W
0x12 R
0x13 R/W
0x14
ADDR
13