STE2004SDIE2 STMicroelectronics, STE2004SDIE2 Datasheet
STE2004SDIE2
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STE2004SDIE2 Summary of contents
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Features ■ 102 x 65 bits display data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ X,Y programmable carriage return ■ Dual partial display mode ■ Row by row scrolling ■ N-line inversion ■ Automatic data RAM blanking ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STE2004S 6 ID-number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram 1 Block diagram Figure 1. STE2004S block diagram OSC_IN OSC_OUT FR_IN SLAVE SYNC FR_OUT BIAS VOLTAGE VSENSE SLAVE HIGH VOLTAGE VLCD VLCDSENSE RES VSSAUX VDD1 I2C BUS SA1 SAO 4/ C101 TIMING OSC GENERATOR ...
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STE2004S 2 Pin description Table 1. Pin description N° Pad Type 1 R64 109-141 C0 to C101 6-107 V 192-203 GND SS V 156-163 Supply IC positive power supply DD1 V 164-171 Supply Internal generator supply voltages. DD2 ...
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Pin description Table 1. Pin description (continued) N° Pad Type SCLK - SCL 181 SDA_OUT 178 SA0 149 SA1 148 DB0 to DB7 182-189 R 175 176 176 RES 172 D/C 174 ...
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STE2004S Figure 2. Chip mechanical drawing MARK_1 ROW 5 ROW 0 COL 0 MARK_3 STE2004S COL 50 (0,0) Y COL 51 X MARK_4 COL 101 ROW 32 ROW 37 MARK_2 Pin description ROW28 ROW31 FR_OUT OSC_OUT VLCD VLCDSENSE VSS TEST_MODE ...
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Pin description Figure 3. Improved ALTH and PLESKO driving method V LCD ROW LCD ROW ...
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STE2004S 3 Circuit description 3.1 Supplies voltages and grounds V supplies voltages to the internal voltage generator (see below). If the internal voltage DD2 generator is not used, this should be connected to V IC. V supply voltage could be ...
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Circuit description the master configuration. The only recognized configuration is Vop=0 that forces the charge pump off state whatever is the value of Vsense_aux. To synchronize the master and slave timing circuits, the slave driver FR_IN pad ...
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STE2004S Figure 6. Bias level generator providing an 1/(n+4) ratio, with n calculated from: For 1/9 ratio is set. For m = 49, n =4, a 1/8 ratio is set. The STE2004S provides ...
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Circuit description Table 3. Bias level m=65 and m=49 Symbol 3.6 LCD voltage generation The LCD voltage at reference temperature (To = 27°C) can be set using the VOP register content according to the ...
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STE2004S 3.7 Temperature coefficients As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, the LCD voltage must be varied with temperature. STE2004S provides eight different temperature coefficients to change the VLCD in a ...
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Circuit description 3.8 Display data RAM The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons. RAM ...
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STE2004S When MY=0, the icon Row is output on R64 in MUX 65 mode, on R56 in MUX 49, and on R48 in MUX33. When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever the MUX rate. ...
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Circuit description Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored format (MX=1) 101 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 Figure 11. Automatic data ...
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STE2004S Figure 13. Automatic data RAM writing sequence with X-Y carriage return (V=1; MX=0) 0 BANK 0 BANK 1 BANK 2 Y CARR BANK 7 BANK 8 Figure 14. Automatic data RAM writing sequence with X-Y carriage return (V=0; MX=1) ...
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Circuit description Figure 16. Data RAM Byte organization with MSB BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 LSB BANK 5 BANK 6 BANK 7 BANK 8 Figure 17. Data RAM byte organization with D0 ...
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STE2004S Figure 18. Memory rows vs. row drivers mapping ICON_MODE=1 and MUX 65 Y Address Y-CARRIAGE address ...
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Circuit description Figure 19. Memory rows vs. row drivers mapping ICON_MODE=0 and MUX 65 Y Address Y-CARRIAGE ...
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STE2004S Figure 20. Memory rows vs. Row drivers mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49 Y Address Y-CARRIAGE address COL Output ...
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Circuit description Figure 21. Memory rows vs. row drivers ;apping ICON_MODE=0, Y-Carriage<=6 and MUX 49 Y Address Y-CARRIAGE ...
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STE2004S Figure 22. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=7, scrolling pointer>07h and MUX 49 Y Address Y-CARRIAGE ...
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Circuit description Figure 23. Memory rows vs. row drivers mapping ICON_MODE=1, Y-Carriage=7, scrolling pointer>07h and MUX 49 Y Address Y-CARRIAGE 0 1 ...
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STE2004S Figure 24. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage=8, Scrolling pointer<10h and MUX 49 Y Address Y-CARRIAGE 0 ...
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Circuit description Figure 25. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=8, Scrolling pointer<10h and MUX 49 Y Address Y-CARRIAGE ...
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STE2004S Figure 26. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage<=4 and MUX33 Y Address Y-CARRIAGE address ...
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Circuit description Figure 27. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage<=4 and MUX 33 Y Address Y-CARRIAGE ...
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STE2004S Figure 28. Row drivers vs. LCD panel interconnection in MUX65 mode Figure 29. Row drivers vs. LCD panel interconnection in MUX49 mode ICON MUX 65 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 ...
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Circuit description Figure 30. Row drivers vs. LCD panel interconnection in MUX33 mode 30/79 ICON MUX 33 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 ROW DRIVERS R40 R41 R42 R43 R44 STE2004S R45 R46 R47 R48 R49 ...
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STE2004S 4 Bus interfaces To provide the widest flexibility and ease of use the STE2004S features six different methods for interfacing the host controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to ...
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Bus interfaces limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device ...
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STE2004S Figure 32. Acknowledgment on the I SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 4.1.1 Communication protocol The STE2004S status read are allowed. The STE2004S has four device addresses. All have the first ...
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Bus interfaces Reading mode If the R/W bit is set to logic 1 the chip outputs data immediately after the slave address. If the D/C bit during the last write access is set to a logic 0, the byte read ...
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STE2004S Figure 36. . SDOUT is in high impedance in steady state and during data write possible to short circuit SDOUT and SDIN and read the I2C address or status byte without any additional lines. Figure 34. 4-lines ...
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Bus interfaces Figure 37. 4-lines SPI reading sequence 4.2.2 3-lines SPI interface The STE2004S 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals (SDIN,SDOUT), one ...
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STE2004S Throughout SDOUT can be read the driver I command sequence that allows to read I Figure 39. and Figure 40. If the R bit is set to logic 0 and D/C=0, the I 1 and D/C=0, the the I ...
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Bus interfaces Figure 40. 3-lines SPI reading sequence 4.2.3 3-lines 9 bits serial interface The STE2004S 3-lines serial interface is a bidirectional link between the display driver and the application supervisor. It consists of three lines: one/two for data signals ...
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STE2004S It is possible to short circuit SDOUT and SDIN, and read the I without any additional line. Figure 41. 3-lines serial bus protocol - one byte transmission CS SCLK SDIN SD/C Figure 42. 3-lines serial bus protocol - several ...
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Bus interfaces Figure 44. 3-lines serial reading sequence 4.3 Parallel interface The STE2004S selectable parallel interfaces are 68000-series and 8080-series. They are both an 8-bits bi-directional link between the display driver and the application supervisor. Both parallel interfaces can be ...
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STE2004S Figure 45. 68000-series parallel interface protocol - one byte transmission Figure 46. 68000-series parallel interface bus protocol - several bytes transmission CS R/W D Figure 47. 68000-series parallel interface protocol in reading mode CS R/W ...
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Bus interfaces Figure 48. 68000-series parallel interface protocol in reading mode (several bytes) CS D/C R 4.3.2 8080-series parallel interface low after the positive edge of RES, the 8080 parallel interface is ready ...
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STE2004S Figure 50. 8080-series parallel bus protocol - several bytes transmission CS D Figure 51. 8080-series parallel interface protocol in reading mode Figure 52. 8080-series parallel interface protocol in reading mode (several bytes) CS D/C ...
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Instruction set 5 Instruction set Two different instructions formats are provided: – With D/C set to LOW : commands are sent to the control circuitry. – With D/C set to HIGH : the data RAM is addressed. Two different instruction ...
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STE2004S Table 8. STE2001/2-like instruction set Instruction D/C R/W H=1 Checker board 0 0 Duty select 0 0 Data order 0 0 Bias ratios 0 0 Reserved 0 0 Set Table 9. Extended ...
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Instruction set Table 9. Extended instruction set Instruction D/C R/W H=[0;1] Checker board select 0 0 Data order 0 0 Bias ratios 0 0 Read mode Set H=[1;0] Driver ...
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STE2004S Table 10. Explanations of Table 8 and Table 9 symbols Bit DIR Scroll by one down H[0] Select page 0 PD Device fully working V Horizontal addressing MX Normal X axis addressing Image is displayed not vertically MY mirrored ...
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Instruction set Table 14. Vlcd range selection PRS[ Table 15. Multiplexing ratio M[ Table 16. Temperature coefficient (T0, T1, T2 ...
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STE2004S Table 18. Charge pump multiplication factor CP2 CP1 Table 19. Bias ratio BS2 BS1 ...
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Instruction set Table 21. Partial display configuration PD2 PD1 Table 22. N-Line inversion NW3 NW2 ...
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STE2004S 5.2 Power down ( power down, all LCD outputs are kept at V generator are off (V disconnected). The internal oscillator is in off state. An external clock can be provided. The RAM contents is not ...
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Instruction set If the DIR bit is set to a logic 0, the offset register is increased by one and the raster is scrolled from top down. If the DIR bit is set to a logic 1, the offset register ...
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STE2004S Figure 54. Dual partial display mode configuration or duty change Table 24. Partial display configurations PDC2 PDC1 SETUP PARTIAL DISPLAY CONFIGURATION SET Driver ...
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ID-number 6 ID-number The STE2004S lets you program a driver identification number (ID-Number), so more than one LCD module with different configuration parameters can be managed on one platform. There are four programmable device ID-numbers: 00111100, 00111101, 0011110 and 0011111. ...
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STE2004S Figure 57. 4-lines SPI interface interconnection in master slave mode RES Figure 58. 8080-series and 68000-series interface interconnection in master slave mode RES STE2004S RES CS D/C SCLK SDIN SDOUT MASTER D/C SCLK SD SLAVE CS CS STE2004S CS ...
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ID-number Figure 59. Host processor interconnection with I2C interface Figure 60. Host processor interconnection with 4-line SPI interface 56/79 VSS TEST_MODE VSSAUX D0 STE2004S SCLK -SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX ...
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STE2004S Figure 61. Host processor interconnection with 3-line SPI interface Figure 62. Host processor interconnection with 3-line serial interface VSS TEST_MODE VSSAUX D0 STE2004S SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX R/W ...
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ID-number Figure 63. Host processor interconnection with 8080-series parallel interface Figure 64. Host processor interconnection with 6800 58/79 VSS TEST_MODE VSSAUX D0 STE2004S SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX R/W - ...
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STE2004S Figure 65. Application schematic using the internal LCD voltage generator and two separate supplies V DD2 1µ 1µF Figure 66. Application schematic using the internal LCD voltage generator and a single supply V DD 1µ ...
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ID-number Figure 67. Power-ON timing diagram VDD2 VDD1 RES CS SCLK SDIN D HOST DRIVER SCL- SDAIN SDOUT - SDA OUT OSCIN, FR_IN (HOST) OSC OUT, FR_OUT (DRIVER) 60/ vdd ...
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STE2004S Figure 68. Power-OFF timing diagram VDD2 VDD1 RES CLK-SCL SDIN-SDAIN D R HOST DRIVER SDOUT SDA-OUT OSCIN (HOST) OSC OUT FR_OUT (DRIVER) FR_IN T VDD Hi-Z Hi-Z RESET TABLE LOADED LR0207 ...
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ID-number Figure 69. Initialization with built-in booster 62/79 SETUP NORMAL DISPLAY MODE CONFIGURATION SET Driver in Power Down(PD=1) SET Driver in Normal Display Mode (PE=0) SET Operative Voltage for Normal Display Operation ( Vop[6:0] - PRS[1;0]) SET Bias Raio for ...
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STE2004S Figure 70. Data RAM to display mapping DISPLAY DATA RAM bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 Table 25. Test pin configuration TEST_MODE ICOR ROW Test Pin TEST_VREF GLASS TOP VIEW DISPLAY DATA RAM ...
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Electrical characteristics 7 Electrical characteristics 7.1 Absolute maximum ratings Table 26. Absolute maximum ratings Symbol V Supply voltage range DD1 V Supply voltage range DD2 V LCD supply voltage range LCD I Supply current SS V Input voltage (all input ...
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STE2004S Table 27. DC operation (continued) Symbol Parameter Voltage generator supply I(V ) DD2 current I(V ) Total supply current DD1,2 External LCD supply I(V ) LDCIN voltage current Logic outputs High logic level output V 0H voltage Low logic ...
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Electrical characteristics Table 27. DC operation (continued) Symbol Parameter Column and row driver R ROW output resistance row Column output R col resistance Column bias voltage V col accuracy Row bias voltage V row accuracy LCD supply voltage LCD supply ...
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STE2004S 7.3 AC operation VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =25°C; unless otherwise specified. Table 28. AC operation Symbol Parameter Figure 71 Internal oscillator ...
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Electrical characteristics Table 28. AC operation Symbol Parameter T Rise time of SCLH signal Cb = 100pF r;DA T Fall time of SDAH signal f;DA T Rise time of SDAH signal Cb = 400pF r;DA T Fall time of SDAH ...
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STE2004S Table 28. AC operation Symbol Parameter Figure 75 Serial interface ( ) F Clock frequency SCLK T Clock cycle SCLK CYC T SCLK pulse width HIGH PWH1 T SCLK pulse width LOW PWL1 T CS setup time S2 T ...
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Electrical characteristics Figure 71. Reset timing diagram VDD2 VDD1 RES INPUTS I/O (HOST) I/O (DRIVER) INTERFACE OUTPUT OSCIN FR_IN (HOST) OSC OUT FR_OUT (DRIVER) 2 Figure 72. I C-bus timings t SDAH t SU;STA SCLH 70/79 Tw(res) Hi-Z Hi-Z RESET ...
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STE2004S Figure 73. 68000-series parallel interface timing D/C R (Write (Read) Figure 74. 8080-series parallel interface timing D (Write (Read SU(A) ...
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Pad coordinates Figure 75. Serial interface timing CS D/C SCLK SDIN SOUT 8 Pad coordinates See Table 29: Pad coordinates 72/ PWL1 WH1 ...
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STE2004S Table 29. Pad coordinates o N Name ...
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Pad coordinates Table 29. Pad coordinates o N Name 67 C60 68 C61 69 C62 70 C63 71 C64 72 C65 73 C66 74 C67 75 C68 76 C69 77 C70 78 C71 79 C72 80 C73 81 C74 82 ...
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STE2004S Table 29. Pad coordinates o N Name 133 R56 134 R57 135 R58 136 R59 137 R60 138 R61 139 R62 140 R63 141 R64/ICON 142 VDD1 AUX 143 FR IN 144 OSC IN 145 Vsns_Slave 146 TEST_VREF 147 ...
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Pad coordinates Table 29. Pad coordinates o N Name 199 VSS 200 VSS 201 VSS 202 VSS 203 VSS 204 VLCD_SNS 205 VLCD 206 VLCD 207 VLCD 208 VLCD 209 VLCD 210 OSC_OUT 211 FR_OUT 212 R31 213 R30 214 ...
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STE2004S Figure 76. Alignment marks dimensions Table 31. Bumps Bumps size Pad size Pad pitch Spacing between bumps Table 32. Die mechanical dimensions Die Size ( Wafers thickness 35 µm 85 µm Dimensions 28µmX97µmX17.5µm 35µm X 104µm 45µm ...
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Ordering information 9 Ordering information Table 33. Ordering information Part numbers STE2004S DIE2 10 Revision history Table 34. Document revision history Date 24-Jan-2006 12-Dec-2006 31-Jan-2007 78/79 Bumped dice on waffle pack Revision 1 Initial release. – Junction temperature range in ...
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... STE2004S Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...