P3Z22V10 NXP Semiconductors, P3Z22V10 Datasheet - Page 5

• Manufacturer Part Number: P3Z22V10
• Description: 3v Zero Power, Totalcmos, Universal Pld Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The P3Z22V10 implements logic functions as sum-of-products
expressions in a programmable-AND/fixed-OR logic array.
User-defined functions are created by programming the connections
of input signals into the array. User-configurable output structures in
the form of I/O macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The P3Z22V10 architecture is illustrated in Figure 1. Twelve
dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs
for creation of logic functions. At the core of the device is a
programmable electrically-erasable AND array which drives a
fixed-OR array. With this structure, the P3Z22V10 can implement up
to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an I/O macrocell
which can be independently programmed to one of 4 different
configurations. The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions with either
Active-High or Active-Low polarity.
AND/OR Logic Array
The programmable AND array of the P3Z22V10 (shown in the Logic
Diagram) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
44 input lines:
– 24 input lines carry the True and Complement of the signals
– 20 additional lines carry the True and Complement values of
1997 Jul 18
applied to the 12 input pins
feedback or input signals from the 10 I/Os
3V zero power, TotalCMOS , universal PLD device
OUTPUT
MACRO
CELL
F0
8
1
OUTPUT
MACRO
CLK/I0
CELL
F1
10
OUTPUT
MACRO
CELL
F2
12
OUTPUT
MACRO
CELL
F3
14
Figure 1.
OUTPUT
MACRO
PROGRAMMABLE AND ARRAY
CELL
F4
16
Functional Diagram
5
(44
OUTPUT
MACRO
132 product terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16)
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset product term
– 1 global asynchronous clear product term
At each input-line/product-term intersection there is an EEPROM
memory cell which determines whether or not there is a logical
connection at that intersection. Each product term is essentially a
44-input AND gate. A product term which is connected to both the
True and Complement of an input signal will always be FALSE, and
thus will not affect the OR function that it drives. When all the
connections on a product term are opened, a Don’t Care state exists
and that term will always be TRUE.
Variable Product Term Distribution
The P3Z22V10 provides 120 product terms to drive the 10 OR
functions. These product terms are distributed among the outputs in
groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic
Diagram). This distribution allows optimum use of device resources.
CELL
132)
F5
used to form logical sums
16
OUTPUT
MACRO
CELL
F6
14
OUTPUT
MACRO
CELL
F7
12
OUTPUT
MACRO
CELL
F8
11
10
I1 – I11
P3Z22V10
OUTPUT
MACRO
Product specification
CELL
F9
8
SP00060A