HY27UF082G2A Hynix Semiconductor, HY27UF082G2A Datasheet
HY27UF082G2A
Available stocks
Related parts for HY27UF082G2A
HY27UF082G2A Summary of contents
Page 1
... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash HY27UF082G2A HY27UF162G2A HY27UF(08/16)2G2A Series 1 ...
Page 2
Document Title 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Memory Revision History Revision No. 0.01 Initial Draft. 1) Change NOP 0.1 2) Correct 5th Read ID 3) Chnage AC Timing Characteristics 0.2 1) Add x16 features. 1) Chnage AC Timing Characteristics tR Before ...
Page 3
... CHIP ENABLE DON’T CARE - Simple interface sith microcontroller SERIAL NUMBER OPTION DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC years Data Retention PACKAGE - HY27UF(08/16)2G2A-T(P) : 48-pin TSOP1( 1.2 mm) - HY27UF(08/16)2G2A-T (Lead) - HY27UF(08/16)2G2A-TP (Lead Free) - HY27UF082G2A-UP : 52-ULGA ( 0.65 mm) - HY27UF082G2A-UP (Lead Free) 3 ...
Page 4
... A cache read feature (x8) is also implemented. This feature allows to dramatically improve the read through- put when consecutive pages have to be streamed out. The HYNIX HY27UF(08/16)2G2A series is available TSOP1 mm, 52-ULGA mm. 1.1 Product List PART NUMBER HY27UF082G2A HY27UF162G2A Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash ORIZATION ...
Page 5
IO15 - IO8 IO7 - IO0 CLE ALE R/B Vcc Vss NC Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure1: Logic Diagram Data Inputs / Outputs (x16 Only) Data Inputs / Outputs Command latch ...
Page 6
Figure 2. 48TSOP1 Contactions, x8 and x16 Device Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 6 ...
Page 7
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 3. 52-ULGA Contactions, x8 Device (Top view through package) HY27UF(08/16)2G2A Series 7 ...
Page 8
PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE). ...
Page 9
IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 NOTE must be set to Low. IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 5th Cycle A27 ...
Page 10
CLE ALE ( NOTE: 1. With ...
Page 11
BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
Page 12
DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read ...
Page 13
Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A18 to A28 (X8) or A17 to A27 (x16) is valid ...
Page 14
Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...
Page 15
Cache program Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (x16) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial ...
Page 16
Cache Read (x8) Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st ...
Page 17
OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V version). WP pin ...
Page 18
Parameter Symbol Valid Block Number NOTE: 1. The 1st block is guaranteed valid block cycles with ECC. (1bit/528bytes) Symbol Ambient Operating Temperature (Temperature Range Option Ambient Operating Temperature (Industrial Temperature Range) ...
Page 19
Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 4: Block Diagram 19 ...
Page 20
Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Leve Output Low Current (R/B) Table 9: DC ...
Page 21
Item Input / Output Capacitance Input Capacitance Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Dummy Busy Time for Cache Program Number of partial Program Cycles in the same page Block Erase Time Table 12: Program / Erase Characteristics ...
Page 22
Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Address to Data Loading time ...
Page 23
... Ready/Busy 6 Ready/Busy 7 Write Protect DEVIIDENTIFIER CYCLE 1st 2nd 3rd 4th 5th Part Number Voltage Width HY27UF082G2A 3.3V HY27UF162G2A 3.3V Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Block Erase Pass / Fail Ready/Busy Ready/Busy Ready/Busy Ready/Busy Write Protect Write Protect Table 14: Status Register Coding ...
Page 24
Description 1 2 Die / Package 4 Reserved Single Level 2x Multi-level String Type Reserved Reservedl 1 Number of 2 Simultaneously 3 Programmed Pages 4 Interleave Program Not Support Between different dice Support Not Support Write Cache Support Table 17: ...
Page 25
Description 1 2 Plane Number 3 4 1Gb 2Gb 4Gb Plane Size 8Gb (Without Redundant Reserved Area) Reserved Reserved Reserved Reserved Table 19: 5th Byte of Device Identifier Description Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash ...
Page 26
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 5: Command Latch Cycle Figure 6: Address Latch Cycle HY27UF(08/16)2G2A Series 26 ...
Page 27
I/Ox t R/B Notes : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.4 / Mar. ...
Page 28
CLE I/O x Figure 10: Read1 Operation (Read One Page) Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash t CLR t CLS t CLH WHR ...
Page 29
Figure 11: Read1 Operation intercepted by CE Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 29 ...
Page 30
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 12 : Random Data output HY27UF(08/16)2G2A Series 30 ...
Page 31
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 13: Page Program Operation HY27UF(08/16)2G2A Series 31 ...
Page 32
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 14 : Random Data In HY27UF(08/16)2G2A Series 32 ...
Page 33
Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 15 : Copy Back Program HY27UF(08/16)2G2A Series 33 ...
Page 34
Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 16 : Cache Program 34 ...
Page 35
Figure 17: Block Erase Operation (Erase One Block) Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 18: Read ID Operation HY27UF(08/16)2G2A Series 35 ...
Page 36
Figure 19: start address at page start :after 1st latency uninterrupted data flow Figure 20: exit from cache read in 5us when device internally is reading (x8) Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 36 ...
Page 37
System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microporcessor. The only function that was removed ...
Page 38
Figure 24: Power On and Data Protection Timing Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 23: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UF(08/16)2G2A Series 38 ...
Page 39
Figure 25: Ready/Busy Pin electrical specifications Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash 39 ...
Page 40
Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
Page 41
Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 27~30) Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 27: ...
Page 42
Rev 0.4 / Mar. 2007 HY27UF(08/16)2G2A Series 2Gbit (256Mx8bit/128Mx16bit) NAND Flash Figure 29: Enable Erasing Figure 30: Disable Erasing 42 ...
Page 43
Figure 31: 48pin-TSOP1 20mm, Package Outline Symbol alpha Table 21: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND Flash millimeters ...
Page 44
Figure 32. 52-ULGA 17mm, Package Outline Symbol CP1 CP2 Table 22: 52-ULGA 17mm, Package Mechanical Data Rev 0.4 / Mar. 2007 2Gbit (256Mx8bit/128Mx16bit) NAND ...
Page 45
MARKING INFORMATION - ...