HY27UF084G2B Hynix Semiconductor, HY27UF084G2B Datasheet - Page 12

• Manufacturer Part Number: HY27UF084G2B
• Description: 4gb Nand Flash
• Manufacturer: Hynix Semiconductor

1
HY27UF(08/16)4G2B Series
4Gbit (512Mx8bit) NAND Flash
3.3 Multi Plane Program.
Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-
lowed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st
plane (A<18>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device
supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h)
stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h
command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page
must be within 2nd plane (A<18>=1). The data of 2nd page other than those to be programmed do not need to be
loaded. Program Confirm command (10h) makes parallel programming of both pages start. User can check operation
status by R/B pin or read status register command, as if it were a normal page program; status register command is
also available during Dummy Busy time (tDBSY). In case of fail in 1st or 2nd page program, fail bit of status register
will be set: Device supports pass/fail status of each plane. Figure 19 details the sequence.
3.4 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in there cycles initiated by an
Erase Setup command (60h). Only address A18 to A29 is valid while A12 to A17 is ignored (x8). The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two step sequence of
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase
and erase verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When
the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 18 details the sequence.
3.5 Multi Plane Erase.
Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multiplane erase
does not need any Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for
multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for mul-
tiple plane program. Figure 20 details the sequence
Rev 0.4 / Jan. 2008
12