HY27UF084G2M Hynix Semiconductor, HY27UF084G2M Datasheet
HY27UF084G2M
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HY27UF084G2M Summary of contents
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... NAND FLASH This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash HY27UF084G2M HY27UF084G2M Series 1 ...
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... Add Marking Information. 6) Correct Address Cycle Map. 7) Correct PKG dimension (TSOP PKG) CP Before 0.050 After 0.100 8) Delete the 1.8V device’s features. Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash History LI, LO HY27UF084G2M Series Draft Date Remark Dec. 2004 Initial Aug. 08. 2005 Preliminary 2 ...
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... HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash -Continued- Draft Date tCEA 25 35 tRP tRC 12 25 Oct. 08. 2005 15 30 Nov. 16. 2005 Jun. 20. 2006 Jul. 10. 2006 Oct. 02. 2006 Dec. 26. 2006 Remark ...
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... Cost effective solutions for mass storage applications NAND INTERFACE - x8 width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27UF084G2M Memory Cell Array = (2K+ 64) Bytes x 64 Pages x 4,096 Blocks PAGE SIZE - x8 device : ( spare) Bytes : HY27UF084G2M BLOCK SIZE ...
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... SUMMARY DESCRIPTION The HYNIX HY27UF084G2M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased ...
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... WE WP R/B Vcc Vss NC Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Table 1: Signal Names HY27UF084G2M Series 6 ...
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... Figure 2. 48TSOP1 Contactions, x8 Device Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 7 ...
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... Figure 3. 52-ULGA Contactions, x8 Device (Top view through package) Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 8 ...
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... A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Description Table 2: Pin Description HY27UF084G2M Series 9 ...
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... FFh - 80h 10h 85h 10h 80h 15h 60h D0h 70h - 85h - 05h E0h 00h 31h 34h - Table 4: Command Set HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash IO4 IO5 IO6 (1) (1) ( A16 A17 A18 A24 A25 A26 (1) (1) (1) L ...
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... 0V/Vcc Table 5: Mode Selection HY27UF084G2M Series MODE Command Input Read Mode Address Input(5 cycles) Command Input Write Mode Address Input(5 cycles) Data Input Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) ...
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... Write Protect pin is not latched by Write Enable to ensure the pro- tection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 12 ...
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... The command register remains in Read Sta- tus command mode until another valid command is written to the command register. Figure 14 details the sequence. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 1 ...
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... On the same plane, It’s prohibited to operate copy-back program from an odd address page (source page even address page (target page) or from an even address page (source page odd address page (target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 14 ...
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... If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to figure 25. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 15 ...
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... Program time for the last page+ Program time for the ( last -1 )th page - (Program command cycle time + Last page data loading time) The value for A29 from second to the last page address must be same as the value given to A29 in first address. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 16 ...
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... If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. Random data output is not available in cache read. Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 17 ...
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... The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 18 ...
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... Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev. 0.7 / Dec. 2006 Min N 4016 VB Table 6: Valid Blocks Number Parameter Table 7: Absolute maximum ratings HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash Typ Max 4096 Value 3. - ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 4: Block Diagram HY27UF084G2M Series 20 ...
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... Vcc (max Vcc (max) LO OUT =-400uA =2.1mA =0.4V OL (R/B) Table 9: AC Conditions HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 3.3Volt Min Typ Max - ± ± 10 Vccx0.8 - Vcc+0.3 -0.3 - Vccx0.2 2 ...
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... Block Erase Time Table 11: Program / Erase Characteristics Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Symbol Test Condition C V = Symbol Main Array NOP Spare Array NOP t HY27UF084G2M Series Min Max - Min Typ Max - 200 700 PROG - 3 700 CBSY - 5 - RBSY - - 4 ...
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... Table 12: AC Timing Characteristics HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 3.3Volt Min Max 100 100 ...
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... Page Size, Block Size, Spare Size, Organization Table 14: Device Identifier Coding 1st cycle Bus Width (Manufacture Code) x8 ADh Table 15: Read ID Data Table HY27UF084G2M Series Cache CODING Read Pass: ‘0’ Fail: ‘1’ Pass: ‘0’ Fail: ‘1’ (Only for Cache Program, else Don’t care) P/E/R Active: ‘ ...
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... Serial Access Time Reserved Reserved 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Table 17: 4th Byte of Device Identifier Description Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash IO7 IO6 IO5 IO4 IO7 ...
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... Rev. 0.7 / Dec. 2006 Figure 5: Command Latch Cycle HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 26 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 6: Address Latch Cycle Figure 7. Input Data Latch Cycle HY27UF084G2M Series 27 ...
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... Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Figure 9: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L) Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 28 ...
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... Figure 11: Read1 Operation (Read One Page) Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 10: Status Read Cycle HY27UF084G2M Series 29 ...
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... Figure 12: Read1 Operation intercepted by CE Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 30 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 13 : Random Data output HY27UF084G2M Series 31 ...
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... Rev. 0.7 / Dec. 2006 Figure 14: Page Program Operation HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 32 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 15 : Random Data In HY27UF084G2M Series 33 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 16 : Copy Back Program HY27UF084G2M Series 34 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 17 : Cache Program HY27UF084G2M Series 35 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 18 :Cache Read RE high HY27UF084G2M Series 36 ...
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... Figure 19: Block Erase Operation (Erase One Block) Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 20: Read ID Operation HY27UF084G2M Series 37 ...
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... Figure 21: start address at page start :after 1st latency uninterrupted data flow Figure 22: exit from cache read in 5us when device internally is reading Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 38 ...
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... So possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function. Figure 23: Program Operation with CE don’t-care. Figure 24: Read Operation with CE don’t-care. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 39 ...
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... Figure 26: Power On and Data Protection Timing Rev. 0.7 / Dec. 2006 Figure 25: Reset Operation VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 40 ...
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... Figure 27: Ready/Busy Pin electrical specifications Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 41 ...
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... Figure 28 : page programming within a block Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 42 ...
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... Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation. Operation Erase Program Read Figure 29: Bad Block Management Flowchart Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Recommended Procedure Block Replacement Block Replacement or ECC (with 1bit/512byte) ECC (with 1bit/512byte) Table 18: Block Failure HY27UF084G2M Series 43 ...
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... Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 30~33) Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 30: Enable Programming Figure 31: Disable Programming HY27UF084G2M Series 44 ...
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... Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash Figure 32: Enable Erasing Figure 33: Disable Erasing HY27UF084G2M Series 45 ...
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... Addressing for program operation Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random address programming is prohibited. See Fig. 34. Rev. 0.7 / Dec. 2006 HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash 46 ...
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... Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev. 0.7 / Dec. 2006 millimeters Min 0.050 0.980 0.170 0.100 11.910 19.900 18.300 0.500 20mm, Package Mechanical Data HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash Typ Max 1.200 0.150 1.030 0.250 0.200 0.100 12.000 12.120 20.000 20.100 18 ...
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... Figure 35. 52-ULGA 17mm, Package Outline Symbol CP1 CP2 Table 20: 52-ULGA 17mm, Package Mechanical Data Rev. 0.7 / Dec. 2006 4Gbit (512Mx8bit) NAND Flash (Top view through package) Min 16.90 11.90 0.55 0.65 0.95 HY27UF084G2M Series millimeters Typ Max 17.00 17.10 13.00 12.00 12.00 12.10 10.00 6.00 1.00 1.50 2.00 1.00 1.00 0.60 0.65 0.70 0.75 1.00 1.05 48 ...
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... C (0 ℃ 0℃ (-2 5℃ 5℃ (-3 0℃ ℃ ), I(-4 0℃ 5℃ (In clu lock ), lock ), ck) : Fixe d Ite -fixe d Ite m HY27UF084G2M Series 4Gbit (512Mx8bit) NAND Flash ...