MT18HTF25672PZ Micron Semiconductor Products, MT18HTF25672PZ Datasheet - Page 10

• Manufacturer Part Number: MT18HTF25672PZ
• Description: Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 8: DDR2 I
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
PDF: 09005aef83dadad1
htf18c256x72pz.pdf - Rev. A 3/10 EN
Parameter
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Active power-down current: All device banks open;
CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (I
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I
= 0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads, I
= 0mA; BL = 4, CL = CL (I
(I
mands; Address bus inputs are stable during deselects; Data bus inputs are switching
DD
RAS =
DD
DD
DD
DD
), AL = 0;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
),
Specifications
t
t
RP =
RRD =
t
RAS MIN (I
t
RP (I
t
t
DD
RRD (I
CK =
), AL = 0;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
t
CK (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
Specifications and Conditions – 2GB
),
t
t
DD
DD
DD
RCD =
DD4W
CK =
t
CK =
),
), AL = 0;
), AL =
t
RC =
t
CK (I
t
t
CK (I
RCD (I
t
RCD (I
t
RC (I
DD
t
DD
CK =
); REFRESH command at every
DD
),
DD
); CKE is HIGH, S# is HIGH between valid com-
DD
t
RAS =
),
t
CK (I
) - 1 ×
t
RAS =
DD
t
RAS MAX (I
t
),
CK (I
t
CK =
t
t
RAS MIN (I
t
2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
CK =
RAS =
t
CK =
DD
t
CK =
t
CK (I
);
t
CK (I
t
OUT
CK =
t
t
t
t
CK (I
RAS MAX (I
CK =
CK =
DD
10
t
DD
CK (I
= 0mA; BL = 4, CL = CL
DD
),
DD
),
t
DD
t
),
CK (I
t
),
RP =
t
CK (I
t
CK (I
); CKE is HIGH, S# is
RAS =
t
DD
t
RCD =
RC =
t
RFC (I
);
DD
t
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RP (I
DD
); CKE is LOW;
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
t
t
); CKE is
RC (I
RAS MAX
),
t
t
RCD (I
DD
RC =
DD
t
RP =
) inter-
); CKE is
DD
t
),
DD
RC
t
OUT
RP
OUT
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
I
I
I
DD2N
DD3N
DD4R
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
© 2010 Micron Technology, Inc. All rights reserved.
I
DD
-80E/
1620
1980
1080
2610
2610
4230
6030
-800
126
900
900
720
180
54
Specifications
1530
1800
2160
2160
3870
5040
-667
126
720
720
540
180
990
54
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA