MT9VDDT1672PHG-265 Micron Semiconductor Products, MT9VDDT1672PHG-265 Datasheet
MT9VDDT1672PHG-265
Related parts for MT9VDDT1672PHG-265
MT9VDDT1672PHG-265 Summary of contents
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DDR SDRAM SMALL-OUTLINE DIMM Features • 200-pin, small-outline, dual in-line memory module (SODIMM) • Supports ECC error detection and correction • Fast data transfer rates: PC2100 and PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 128MB ...
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... Table 2: Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY MT9VDDT1672PHG-335_ 128MB MT9VDDT1672PHY-335_ 128MB MT9VDDT1672PHG-262_ 128MB 128MB MT9VDDT1672PHY-262_ MT9VDDT1672PHG-26A_ 128MB MT9VDDT1672PHY-26A_ 128MB MT9VDDT1672PH(I)G-265_ 128MB 128MB MT9VDDT1672PH(I)Y-265_ MT9VDDT3272PHG-335_ 256MB MT9VDDT3272PHY-335_ 256MB MT9VDDT3272PHG-262_ 256MB MT9VDDT3272PHY-262_ 256MB 256MB MT9VDDT3272PHG-26A_ MT9VDDT3272PHY-26A_ 256MB MT9VDDT3272PH(I)G-265_ ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...
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Table 5: Pin Descriptions Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation. PIN NUMBERS SYMBOL 118, 119, 120 WE#, CAS#, RAS# 35, 37 CK0, CK0# 96 CKE0, 121 117, 116 BA0, BA1 99 (A12), ...
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Table 5: Pin Descriptions Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation. PIN NUMBERS SYMBOL 13, 14, 17, 18, DQ0–DQ63 19, 20, 23, 24, 29, 30, 31, 32, 41, 42, ...
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DM0 DM1 DM2 DM3 DM8 BA0, BA1 A0-A11 (128MB) A0-A12 (256MB, 512MB) A0-A13 (1GB) RAS# CAS# CKE0 WE# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as ...
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General Description The Micron MT9VDDT1672PH, MT9VDDT3272PH, MT9VDDT6472PH, and MT9VDDT12872PH, are high- speed CMOS, dynamic random-access, 128MB, 256MB, 512MB, and 1GB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules ...
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Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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All other combinations of values for A7–A11 (128MB.), A7–A12 (256MB, 512MB), or A7–A13 (1GB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 13: I Specifications and Conditions – 256MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: I Specifications and Conditions – 512MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 15: I Specifications and Conditions – 1GB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 16: Capacitance) Note: 11; notes appear on pages 19–22 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 17: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM components only; ...
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Table 17: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM components only; notes appear on pages 19–22 AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first non- valid, per access Data Hold Skew Factor ACTIVE to ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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However, an AUTO REFRESH command must be asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, 512MB, 1GB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The ...
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HP min is the lesser of CL minimum and t minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be ...
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Random addressing changing and 50 percent of data changing at every transfer. 42. Random addressing changing and 100 percent of data changing at every transfer. 43. CKE must be active (high) during the entire time a refresh command is ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 PARAMETER SYMBOL Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter t Input Clock Slew ...
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Figure 11: Component Case Temperature vs. Air Flow 100 NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...
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Table 19: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT Current Address Read 1 Random Address Read ...
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Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 23: Serial Presence-Detect Matrix – 128MB, 256MB, 512MB “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 ...
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Table 23: Serial Presence-Detect Matrix – 128MB, 256MB, 512MB (Continued) “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 32 Address and Command Setup Time, (see note 4) 33 Address and Command Hold Time, (see note 4) 34 Data/Data ...
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Table 24: Serial Presence- Detect Matrix – 1GB “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number ...
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Table 24: Serial Presence- Detect Matrix – 1GB (Continued) “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW” BYTE DESCRIPTION 32 Address and Command Setup Time, (see note 4) 33 Address and Command Hold Time, (see note 4) 34 Data/Data Mask ...
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Figure 16: 200-Pin SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) U6 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Advance: This datasheet contains initial descrip- ...