TEF6700HL NXP Semiconductors, TEF6700HL Datasheet - Page 31

• Manufacturer Part Number: TEF6700HL
• Description: Car Radio Tuner Front-end For Digital If
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12 I
12.1
SDA and SCL HIGH and LOW levels are specified
according to a 3.3 V I
thresholds of a 5 V bus.
The standard I
following definitions.
IC addresses:
Structure of the I
increment.
Subaddresses are not used.
The second I
connecting pin ADDRSEL via a 120 k resistor to GND.
The third I
pin ADDRSEL via a 33 k resistor to GND.
The maximum bit rate for this device is 100 kbits/s.
The I
BUSENABLE). If pin BUSENABLE is HIGH the
communication with the device is active; if pin
BUSENABLE is LOW the signals on the I
ignored so that higher bit rates (>100 kbits/s) can be used
to communicate with other devices on the same I
The enable signal must not change while bus
communication takes place.
The data hold time t
No default settings at power-on reset. I
transmission is required to program the IC.
12.1.1
Data sequence: address, byte 0, byte 1, byte 2, byte 3,
byte 4, byte 5, and byte 6.
The data transfer has to be in this order. The LSB of the
address being logic 0 indicates a write operation.
Bit 7 of each byte is considered the MSB and has to be
transferred as the first bit of the byte.
The data becomes valid at the output of the internal
latches with the acknowledge of each byte. A STOP
condition after any byte can shorten transmission times.
2003 Oct 21
1st IC address C2H: 1100001 R/W
2nd IC address C0H: 1100000 R/W
3rd IC address C4H: 1100010 R/W.
Car radio tuner front-end for digital IF
2
2
C-BUS PROTOCOL
C-bus interface is extended with an enable input (pin
I
2
C-bus specification
D
2
ATA TRANSFER
C-bus address can be selected by connecting
2
C-bus address can be selected by
2
C-bus specification is expanded by the
2
C-bus logic: slave transceiver with auto
HD;DAT
2
C-bus. The bus pins tolerate also
must be at least 1 s.
2
2
C-bus are
C-bus
2
C-bus.
31
When writing to the transceiver by using the STOP
condition before completion of the whole transfer:
12.1.2
For new frequency setting, in both AM and FM mode, the
programmable divider is enabled by setting bit PRESET to
logic 1. To select a frequency, two I
are necessary:
12.2
12.2.1
Table 1 Write mode
Table 2 Read mode
Notes
1. S = START condition.
2. A = acknowledge.
3. P = STOP condition.
4. NA = no acknowledge.
Table 3 IC address byte
Notes
1. Pin ADDRSEL left open-circuit activates 1st
2. Read or write bit:
ADDRESS
S
S
The remaining bytes will contain the old information
If the transfer of a byte is not completed, this byte is lost
and the previous information is available.
First: bit PRESET = 1
Second: bit PRESET = 0.
(1)
(1)
IC address; R
activates 2nd IC address; R
pin ADDRSEL to ground activates 3rd IC address.
0 = write operation to TEF6700HL
1 = read operation from TEF6700HL.
1
2
3
I
address (write)
2
address (read)
C-bus protocol
F
D
REQUENCY SETTING
ATA TRANSFER MODE AND
1
1
1
ext
1
1
1
= 120 k at pin ADDRSEL to ground
IC ADDRESS
0
0
0
A
A
(2)
(2)
0
0
0
data byte(s)
data byte 0 NA
ext
0
0
0
= 33 k at
IC
2
(1)
C-bus transmissions
Product specification
TEF6700HL
ADDRESS
0
0
1
1
0
0
A
(2)
MODE
(4)
R/W
R/W
R/W
P
P
(3)
(3)
(2)