EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 32

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

Table 7-1.
32
Term
JITTER
TS
ORT
TOD
TDR
TD1
TD2
TC
TPD
TRDR
TR
TF
PSRR
NRZ
IMD
NPR
VSWR
0811A–BDC–12/08
Definition of Terms (Continued)
Aperture uncertainty
Settling time
Digital data output delay
Time delay from data
transition to data ready
Time delay from data ready
to data
Encoding clock period
Pipeline delay
Rise time
Power supply rejection ratio
Nonreturn to zero
Intermodulation distortion
Noise power ratio
Voltage standing wave ratio
Overvoltage recovery time
Data ready output delay
Data ready reset delay
Fall time
Description
Sample to sample variation in aperture delay. The voltage error due to jitter
depends on the slew rate of the signal at the sampling point
Time delay to achieve 0.2% accuracy at the converter output when a 80%
full-scale step function is applied to the differential analog input
Time to recover 0.2% accuracy at the output, after a 150% full-scale step
applied on the input is reduced to midscale
Delay from the rising edge of the differential clock inputs (CLK,CLKB) (zero
crossing point) to the next point of change in the differential output data (zero
crossing) with specified load
Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero
crossing point) to the next point of change in the differential data ready output
(zero crossing) with specified load
General expression is TD1 = TC1 + TDR –TOD with TC = TC1 + TC2 = 1
encoding clock period
General expression is TD2 = TC2 + TDR – TOD with TC = TC1 + TC2 = 1
encoding clock period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2TC2 = Minimum
clock pulse width (low)
Number of clock cycles between the sampling edge of an input data and the
associated output data being made available, (not taking in account the TOD)
Delay between the falling edge of the data ready output asynchronous Reset
signal (DDRB) and the reset to digital zero transition of the data ready output
signal (DR)
Time delay for the output data signals to rise from 20% to 80% of delta
between low level and high level
Time delay for the output data signals to fall from 20% to 80% of delta
between low level and high level
Ratio of input offset variation to a change in power supply voltage
When the input signal is larger than the upper bound of the ADC input range,
the output code is identical to the maximum code and the out -of- range bit is
set to logic one. When the input signal is smaller than the lower bound of the
ADC input range, the output code is identical to the minimum code, and the
out-of-range bit is set to logic one. (It is assumed that the input signal
amplitude remains within the absolute maximum ratings)
The two tones intermodulation distortion (IMD) rejection is the ratio of either
input tone to the worst third order intermodulation products
The NPR is measured to characterize the ADC performance in response to
broad bandwidth signals. When applying a notch-filtered broadband white-
noise signal as the input to the ADC under test, the Noise Power Ratio is
defined as the ratio of the average out-of-notch to the average in-notch power
spectral density magnitudes for the FFT spectrum of the ADC output sample
test
The VSWR corresponds to the ADC input insertion loss due to input power
reflection. For example a VSWR of 1.2 corresponds to a 20 dB return loss
(i.e. 99% power transmitted and 1% reflected)
e2v semiconductors SAS 2008
EV10AS008B