EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 38

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

8.4.2
8.5
8.6
38
Noise Immunity Information
Digital Outputs: Termination and Logic Compatibility
0811A–BDC–12/08
Equivalent Single-ended Clock Inputs Voltage Levels (1 dBm Single ended on 50Ω Recommended)
Figure 8-6.
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip
environment perturbations resulting from the circuit itself or induced by external circuitry (cascode stages
isolation, internal damping resistors, clamps, internal on chip decoupling capacitors).
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced
noise immunity by efficient common mode noise rejection. Common mode noise voltage induced on the
differential analog and clock inputs will be cancelled out by these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount of cou-
pled noise on the active inputs: The analog inputs and clock inputs of the EV10AS008B device have
been surrounded by ground pins, which must be directly connected to the external ground plane.
The EV10AS008B output buffers are designed to drive 50Ω controlled impedance lines properly termi-
nated by a 50Ω resistor. A 10.5 mA bias current flowing alternately into one of the 50Ω resistors when
switching ensures a 0.25V single-ended voltage drop across the resistor (0.5V differential)
Each single-ended output transmission line length must be kept identical (keep < 3 mm). Mismatches in
the differential line lengths may cause output differential common mode variation.
It is recommended to bypass the midpoint of the differential 100Ω termination with a 47 pF capacitor to
avoid common mode perturbation in case of slight mismatch in the differential output line lengths.
See recommended-termination scenarios here below.
• For LVDS digital output logic compatibility, V
Single-ended Clock Input (Ground Common Mode)
+0.5
-0.50
V
PLUSD
CLK
should be tied to 2.5V (±75 mV).
CLKB
0V
t
e2v semiconductors SAS 2008
EV10AS008B