EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 37

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

8.4
8.4.1
e2v semiconductors SAS 2008
Clock Inputs (CLK/CLKB)
Differential Clock Inputs Voltage Levels (4 dBm differential on 100Ω Recommended)
The EV10AS008B clock inputs are designed for either single-ended or differential operation. The
EV10AS008B clock inputs are on- chip 100Ω (2
AC coupled to ground through 40 pF on chip capacitor. Therefore either ground or different common
modes could be used (ECL, LVDS).
However logic ECL or LVDS square wave clock generators are not recommended because of poor jitter
performances.
Furthermore, the propagation times of the biasing tees used to offset the common mode voltage to ECL
or LVDS levels may not match. A very low phase noise (low jitter) sinewave input signal should be used
for enhanced SNR performance, when digitizing high frequency analog inputs.
Typically, using a sinewave oscillator featuring
bal jitter value (including ADC + generator) of less than 200 fs RMS has been measured. If clock signal
frequency is at fixed rates, it is recommended to narrow band filter the clock signal to improve jitter
performance.
But driving the clock input in single ended may perturb the chip ground plane, (since termination mid
point is AC coupled to chip ground plane). Therefore, it is recommended to drive the clock input in differ-
ential, for minimum chip ground plane perturbation (4 dBm max operating recommended). The minimum
operating clock input power is
avoid SNR performances degradations linked to clock signal slew rate. A single to differential balun with
sqrt (2) ratio may be used (featuring 50Ω input impedance with 100Ω differential termination).
Recommended clock inputs common mode is ground.
Figure 8-5.
Differential Clock Inputs (Ground Common Mode): Recommended
+0.25
-0.25
V
–
1 dBm (equivalent to ±100 mV minimum swing on each clock input), to
–
×
CLK
135 dBc/Hz phase noise, at 20 KHz from carrier, a glo-
50Ω) differentially terminated. Termination mid point is
CLKB
0V
t
EV10AS008B
0811A–BDC–12/08
37