EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet - Page 34

• Manufacturer Part Number: EVX10AS008BGL
• Description: Adc Single 2.2gsps 10-bit Lvds 152-pin Cbga
• Manufacturer: ETC-unknow

8.2
8.2.1
8.2.2
34
Principle of Data Ready Signal Control by DRRB Input Command
0811A–BDC–12/08
Data Ready Output Signal Reset
Data Ready Output Signal Restart
interleaved ADCs or using a single ADC with demultiplexed outputs. Without data ready signal initializa-
tion, it is impossible to store the output digital data in a defined order.
When used with e2v AT84CS001 1:2/1:4 10 bit DMUX, it is not required to initialize the data ready, as
this device can start on either clock edge.
The data ready signal is reset on falling edge of DRRB input command. DRRB may also be connected to
ground for data ready output signal Master Reset. As far as DRRB remains at logical low level the data
ready output remains at logical zero (LVDS low) and is independent on the external free running encod-
ing clock.
The data ready output signal (DR,DRB) is reset to logical zero (LVDS low) after TRDR.
TRDR is measured between the +1.15V point of the falling edge of DRRB input command and the zero
crossing point of the differential data ready output signal (DR,DRB).The data ready Reset command may
be a pulse of 1 ns minimum time width.
The Data Ready output signal restarts on DRRB command rising edge, logical high levels.
DRRB may also be connected to 3.3V for normal free running of the Data Ready output signal. The Data
Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB ris-
ing edge instant:
Consequently, as the analog input is sampled on the clock rising edge, the first digitized data corre-
sponding to the first acquisition (N) after Data Ready signal restart (rising edge) is always strobed by the
third rising edge of the data ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero
crossing point) to the rising or falling edge of the differential Data Ready signal (DR,DRB) (zero crossing
point).
Note: For normal initialization of Data Ready output signal, the external encoding clock signal frequency
and level must be controlled.
It is reminded that the minimum encoding clock sampling rate for the ADC is 200 Msps, due to internal
T/H droop rate. Consequently the clock cannot be stopped without corrupting the current held data.
1. The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is low: the
2. The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is high: the
Data Ready output first rising edge occurs after half a clock period on the clock falling edge,
after a typical delay time TDR = 360 ps already defined here above.
Data Ready output first rising edge occurs after one clock period on the clock falling edge, and
a delay TDR = 360 ps.
e2v semiconductors SAS 2008
EV10AS008B