EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 19

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

Figure 2-4.
e2v semiconductors SAS 2009
DMUX
ADC
(A0, A0N)...(A9, A9N)
VIN
ADC CLK
(B0, B0N)...(B9, B9N)
Digital Outputs & Data Ready Signals for Port A, Port B, Port C, Port D:
Digital Data: after TOD1, TOD2, TOD3, TOD4 ; Data Ready Signals: after TDR1, TDR2, TDR3, TDR4
Port A (N) : 4.5 Clock Cycles
(DRA, DRAN) Dual Data rate
Port B (N+1) : 4.5 Clock Cycles
(DRB, DRBN) Dual Data rate
Port C (N+2 ) : 4.5 Clock Cycles
(DRC, DRCN) Dual Data rate
Port D (N+3 ): 4.5 Clock Cycles
(DRD, DRDN) Dual Data rate
(C0, C0N)...(C9, C9N)
Timing Diagram Staggered mode, 1:4 DMUX Ratio
(D0, D0N)...(D9, D9N)
DMUX Odd Latches
ADC Digital
Outputs
DMUX Even Latches
ADC Data Clock
(Fclock / 2)
Port Select B
Port Select A
Port Select C
ADC Fclock / 4
Port Select D
Latches Port A
Latches Port B
Latches : Port C
Latches : Port D
N
N-4
4.5 ADC+DMUX
ADC Pipeline Delay: 4 clock cycles
TA = +350ps
N+1
Data for N
N+1
N-3
N+2
4.5 ADC+DMUX
N - 4
N - 1
N+2 N+3
Data for N+1
N-2
N - 3
N+3
4.5 ADC+DMUX
-2
Data for N+2
N - 2
N-1
4.5 ADC+DMUX
-1
N - 2
N - 3
Data for N+3
N
A B
Port A B C D DMUX Latency : 0.5 clock
N - 1
N
N - 4
TOD1
N+1
1
TOD2
N
N
N+2
C
N + 1
N + 1
2
N+3
D
TOD3
N + 2
TDR1
3
N + 2
TDR2
TOD4
N+4
Pipeline Delay Port A, B ,C ,D : 4.5 clock cycles
4
N + 3
N + 3
N+5
N
N + 4
TDR3
5
N+4
N+6
N+1
N + 5
Tskew
6
N + 5
N+2
N + 6
N + 6
7
TD
N+3
N + 7
1
N + 7
N+4
TD2
EV10AS150A
Tskew
0954B–BDC–12/09
N+5
Tskew
N+6
TD1
N+7
TD2
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