EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 50

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
It is important that a digital power plane does not overlap an analog power plane as can be seen on
Fig-
ure 5-4
a). If this constraint is not respected, this will induce capacitance between the overlapping areas,
which is likely to cause RF emissions to pass from one plane to another.
Figure 5-4.
Overlapping of Analog and Digital Planes
Analog +
Digital +
Analog +
Digital +
Analog -
Digital -
Analog -
Digital -
a) bad
b) correct
Power planes are designed using the same rules as ground planes. Keep the analog supply plane
entirely under the analog ground plane, see on
Figure 5-4 on page
50. This gives an analog supply plane
over the analog ground plane and a digital supply plane over the digital ground plane. In this case, it
could not cause unwanted capacitance between the two planes.
Moreover, power supply pins should be decoupled directly to the ground plane. The ceramic capacitor
should be located as close as possible to the IC power pins.
The sampling clock generation circuitry should be treated like analog circuitry and also be grounded and
heavily-decoupled to the analog ground plane. It also should be isolated from noisy digital circuits.
So, the ground plane not only acts a low impedance return path for decoupling high frequency currents
but also minimizes RF emissions. Because of the shielding action of the ground plane, the circuit’s sus-
ceptibility to external RF is also reduced.
The optimum partitioning for Analog and Digital Power and Ground planes is illustrated in
Figure 5-5 on
page
51.
The isolation between FPGA Ground plane and DGND of ADC is recommended but not mandatory,
depending on switching noise level which may be injected by FPGA.
The AGND and DGND shall be DC connected together by a 0 ohm resistor, and making use of the para-
sitic (high resonant) inductance of the resistor element to reject the HF spikes. Same DC connection
shall be between DGND of ADC and DGND of FPGA if used.
This recommendation for optimum isolation must be followed carefully for optimum rejection of Fclk/4
clock spur in 1:4 DMUX mode.
DGND is only allocated to Output Buffers of ADC and digital section + Digital output buffers of 1:4
DMUX. AGND ground plane is allocated to ADC only, and needs to be isolated from 1:4 DMUX output
buffers switching into 40 differential 100Ω terminations. Switching Noise is mainly generated by back
reflection effects due to L,C parasitics of 100Ω terminations. This leads to switching noise into V
PLUSD
and DGND which gives energy to Fclk/4 clock related spur if fed back to the ADC Ground.
As digital output buffers are of main concern, we essentially have to concentrate on V
and DGND
PLUSD
layout. V
power plane shall not overlap with AGND ground plane and other analog power supplies
PLUSD
planes (V
, V
). Coupling with VCCD is less critical since allocated to the Digital DMUX only, not
CCA5
CCA3
to the ADC analog section.
50
0954B–BDC–12/09
e2v semiconductors SAS 2009