EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 54

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
5.2.3
5.3
54
Clock Input Implementation
0954B–BDC–12/09
Differential versus Single-ended Input: Rejection for Fclk/4 Spurs
If the 1:4 DMUX Ratio is selected, the rejection of the Fclk/4 clock related spur becomes an issue since
the clock spur is located at the middle of the Nyquist zone.
With 1:2 DMUX Ratio, the clock related spur is located at Fclk/2, and does not affect the center of the
band of operation.
The rejection of Fclk/4 becomes 6 dB more efficient if the ADC is differentially driven. (A delta of –6 dB is
measured in differential vs. single-ended for the Fclk/4 level).
On EV10AS150A evaluation board, the measured Fclk/4 level is:
The ADC has been carefully implemented at chip layout level and packaging level to ensure maximum
electric isolation between the noisy Digital output buffers Section and Analog sections of the ADC. (Ana-
log sections include the logic section and the timing circuitry of the ADC).
At application board level:
The absolute value for Fclk/4 in either single-ended or differential mode can be even further improved by
improving the electric isolation of the +2.5V power supply: The +2.5V Power plane dedicated to the 40
Digital Output Buffers drives most of the Fclk/4 switching noise energy, and has to be isolated from the
other remaining power supplies.
Refer to
The EV10AS150A differential clock input buffer is based on fast regeneration amplifiers, in order to fea-
ture a square wave like sampling clock for the Track and Hold, featuring very fast internal slew-rates to
ensure low internal sampling jitter.
The EV10AS150A differential clock input buffer is on-chip 100Ω terminated (50Ω on each single-ended
clock input).
The clock input buffer is biased in the same way as the differential analog input preamplifier:
The differential on-chip clock inputs terminations are based on resistive 55Ω + 550Ω voltage splitter
biased under +3.3V to Ground, providing 5Ω impedance (550Ω // 55Ω = 50Ω) together with 3V internal
DC common mode biasing for both inputs.
• –72 dBFS in single-ended, corresponding to –74 dBm with –2 dBm Full Scale input power (0.5Vpp in
• –78 dBFS in differential, corresponding to –82 dBm with –5 dBm Full Scale input power (0.5Vpp in
However, the THD will be somewhat impacted, since the harmonics are RSS summed since even and
odd harmonics have now similar weightings in single-ended:
The THD is slightly impacted by –1 dB in the 1
MHz).
In the 3
Harmonic impact on THD in single-ended will become much more important (H2 = + 6 dB versus
differential mode):
Therefore in the 3
Spurious Free Dynamic Range (SFDR) and optimum total harmonic distortion performance (THD).
Note: For THD computation, the 10 1
50Ω).
100Ω).
Figure 5-5 on page 51
rd
Nyquist for large signals close to ADC Full Scale, (e.g. Fin = 4000 MHz, –1 dBFS), the 2
rd
Nyquist, it is highly recommended to drive the inputs in differential for optimum
for board layout recommendation for optimum isolation.
st
low rank harmonics are taken into account.
st
Nyquist, and –2 dB in the 2
nd
e2v semiconductors SAS 2009
Nyquist (Fin < 3000
nd