EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 37

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

4.4.3
e2v semiconductors SAS 2009
DMUX Output Data Mode (STAGG)
Figure 4-7.
Table 4-4.
When DRTYPE is left floating, the default mode is DR.
Two output modes are provided:
In staggered mode, the output clock for each port is provided by the DRA, DRAN, DRB, DRBN, DRC,
DRCN and DRD, DRDN signals which corresponds respectively to the AORN, AOR, BORN, BOR,
CORN, COR, DORN and DOR.
The Simultaneous mode is the default mode (STAGG left floating or at logic “1”).
The Staggered mode is activated by the means of the STAGG input (active low).
Figure 4-8.
• Staggered: the output data come out of the DMUX the one after the other;
• Simultaneous: the output data come out of the DMUX at the same time.
Data Out
Data Out Port C
Data Out Port D
Data Out Port A
Data Out Port B
in DR/2 mode
DR/2 Mode
DMUX Output Clock Type Selection Settings
Simultaneous Mode in 1:4 Ratio (STAGG = 1)
DR
in DR mode
DRTYPE
DR
DR
1
0
N + 1
N + 2
N + 3
N
DMUX Output Clock Type
N + 4
N + 5
N + 6
N + 7
DR/2
DR
EV10AS150A
0954B–BDC–12/09
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