EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 44

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Table 4-8.
Notes:
4.5.4
4.5.5
44
Address
0100
0110
1. It is recommended to adjust clock duty cycle at 35/65% to optimize SFDR and THD at high sampling rate in 2
2. It is recommended to adjust clock adjust to +30 ps to optimize SNR in 2
3. SDA Coarse & SDA fine: Total possible = total Coarse + total Fine = 90 + 30 ps = 120 ps
0954B–BDC–12/09
NAP Mode
Binary or Gray Output Mode
zone.
3WSI Settings (Continued)
Table 4-9.
Comments:
The NAP mode is controlled via the 3WSI serial interface, reducing the ADC power dissipation by 0.9W.
When the device is not used, minimal Power consumption for the combined ADC and 1:4 DMUX chips is
obtained by turning on the NAP mode (on ADC part) and the SLEEP mode (DMUX) simultaneously.
It is possible for the user to choose between the Binary or Gray output data format. Gray coding may be
used in order to reduce the effect of BER when occurring, by storing Gray output codes.
Digital Data format selection is made using the 3WSI (default selection is Binary), programming the state
register at address “0110”.
Binary two’s complement is also available asserting bit D6 at 1 of state register at address “0110”.(only
taken in account if bit D5 is asserted at 0, i.e. in Binary output mode).
Setting for Address :0110
Mode SDA OFF
Mode SDA ON
Mode binary output
Mode gray output
Two’s complement OFF
Two’s Complement ON
Data Ready Reset (DRR) inactive High
Data Ready Reset (DRR) inactive Low
NAP Mode OFF
NAP mode ON
1. SDA Mode: to take into account the value of the Sampling Delay Adjust register, bit D3 of the
2. NAP mode of the ADC part reduces its power dissipation (in standby mode, both terminations
State Register
Offset Adjust
Description
state register should be asserted to 1. For applications requiring extremely low clock jitter and
no interleaving of several ADCs, it is recommended to assert bits D3 of state register to 0.
of the differential data output buffers of the ADC are driven at same value).
State Register Description
parameter value
register D7:D0
register D9:D0
Default Value
D9
X
X
0000000000
X
X
X
X
X
X
0
1
10000000
0mV
D8
X
X
X
X
X
X
X
X
0
1
D7
X
X
X
X
X
X
X
X
X
X
Recommended
Value
nd
D6
X
X
X
X
X
X
X
X
0
1
Nyquist zone if not used in interleaving mode.
D5
X
X
0
1
0
0
X
X
X
X
See description hereafter
Max Value
11111111
+20mV
D4
X
X
X
X
X
X
X
X
X
X
D3
X
X
X
X
X
X
X
X
0
1
e2v semiconductors SAS 2009
Min Value
00000000
–20mV
D2
X
X
X
X
X
X
X
X
X
X
nd
D1
X
X
X
X
X
X
X
X
X
X
Nyquist
156 µV
Step
D0
X
X
X
X
X
X
X
X
X
X