MC56F8345 Freescale Semiconductor, Inc, MC56F8345 Datasheet
MC56F8345
Available stocks
Related parts for MC56F8345
MC56F8345 Summary of contents
Page 1
... Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8345 Rev. 17 01/2007 freescale.com ...
Page 2
Version History Rev 1.0 Pre-Release version, Alpha customers only Rev 2.0 Initial Public Release Rev 3.0 Corrected typo in grammar issues. Rev 4.0 Added “Typical Min” values to language throughout family. Updated values in Current Consumption per Power Supply Pin, ...
Page 3
Document Revision History (Continued) Version History Rev 15.0 Updated JTAG ID in Table 2-2. Clarified external reference crystal frequency for PLL in maximum value to 8.4MHz. Rev 16.0 Replaced “Tri-stated” with an explanation in State During Reset column in • ...
Page 4
Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 5
General Description Note: Features in italics are NOT available in the 56F8145 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 128KB Program Flash • 4KB Program ...
Page 6
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 7 1.1. 56F8345/56F8145 Features . . . . . . . . . . ...
Page 7
Part 1 Overview 1.1 56F8345/56F8145 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...
Page 8
Memory Note: Features in italics are NOT available in the 56F8145 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
Page 9
Two dedicated external interrupt pins • 49 General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO • External reset input pin for hardware reset • External reset output pin for system reset • Integrated low-voltage interrupt module • ...
Page 10
Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 ...
Page 11
The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); ...
Page 12
Architecture Block Diagram Note: Features in italics are NOT available in the 56F8145 device and are shaded in the following figures. The 56F8345/56F8145 architecture is shown in 56800E system buses communicate with internal memories and the IPBus Bridge. internal ...
Page 13
JTAG / EOnCE 56800E CHIP TAP Controller TAP Linking Module External JTAG Port cdbr_m[31:0] xdb2_m[15:0 NOT available on the 56F8145 device. * EMI not functional in this package; since only part of the address/data bus is bonded out, use ...
Page 14
CLKGEN (OSC / PLL) Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8145 device. 14 To/From IPBus Bridge SPI1 GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF SPI0 ...
Page 15
Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
Page 16
... Distribution Table 1-3 Chip Documentation Description Logic State True False True False are defined by individual product specifications. 56F8345 Technical Data, Rev. 17 Centers, or online Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM MC56F8345 MC56F8345E MC56F8145E Signal State 1 Voltage Asserted Deasserted Asserted ...
Page 17
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8345 and 56F8145 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
Page 18
Power V V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and XTAL Clock CLKO A8 - A13 (GPIOA0 - 5) * ...
Page 19
Power Power V Power DDA_OSC_PLL Ground Ground Other V CAP Supply V PP Ports CLKMODE PLL and Clock A8 - A13 (GPIOA0 - 5) * External Address GPIOB0-4 (A16 - 20) Bus or GPIO * D7 - D10 (GPIOF0 - ...
Page 20
Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. EMI is not functional in this package; since only part of the address/data bus is bonded out, use as ...
Page 21
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name V 95 Supply SSA_ADC OCR_DIS 71 Input Supply CAP V 2 122 CAP CAP CAP V ...
Page 22
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name CLKO 6 Output A8 15 Output (GPIOA0) Schmitt Input Output (GPIOA1) A10 17 (GPIOA2) A11 18 (GPIOA3) A12 19 (GPIOA4) A13 20 (GPIOA5) ...
Page 23
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name GPIOB4 31 Schmitt Input/ Output (A20) Output (prescaler_ Output clock Input/ Output (GPIOF0) Input/ Output D8 23 (GPIOF1 (GPIOF2) D10 26 ...
Page 24
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name GPIOD0 42 Input/ Output (CS2) Output GPIOD1 43 (CS3) GPIOD2 44 (CS4) GPIOD3 45 (CS5) GPIOD4 46 (CS6) GPIOD5 47 (CS7) TXD0 7 Output (GPIOE0) ...
Page 25
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name RXD1 41 Input (GPIOD7) Input/ Output TCK 115 Schmitt Input TMS 116 Schmitt Input TDI 117 Schmitt Input TDO 118 Output Freescale Semiconductor Preliminary State ...
Page 26
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name TRST 114 Schmitt Input PHASEA0 127 Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output PHASEB0 128 Schmitt Input (TA1) Schmitt Input/ Output (GPIOC5) ...
Page 27
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name INDEX0 1 Schmitt Input (TA2) Schmitt Input/ Output (GPIOC6) Schmitt Input/ Output HOME0 2 Schmitt Input (TA3) Schmitt Input/ Output (GPIOC7) Schmitt Input/ Output SCLK0 ...
Page 28
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name MOSI0 126 Input/ Output (GPIOE5) Input/ Output MISO0 125 Input/ Output (GPIOE6) Input/ Output SS0 123 Input (GPIOE7) Input/ Output 28 State During Signal Description ...
Page 29
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name PHASEA1 9 Schmitt Input (TB0) Schmitt Input/ Output (SCLK1) Schmitt Input/ Output (GPIOC0) Schmitt Input/ Output PHASEB1 10 Schmitt Input (TB1) Schmitt Input/ Output (MOSI1) ...
Page 30
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name INDEX1 11 Schmitt Input (TB2) Schmitt Input/ Output (MISO1) Schmitt Input/ Output (GPIOC2) Schmitt Input/ Output 30 State During Signal Description Reset Input, Index1 — ...
Page 31
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name HOME1 12 Schmitt Input (TB3) Schmitt Input/ Output (SS1) Schmitt Input (GPIOC3) Schmitt Input/ Output PWMA0 58 Output PWMA1 60 PWMA2 61 PWMA3 63 PWMA4 ...
Page 32
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name FAULTA0 67 Schmitt Input FAULTA1 68 FAULTA2 69 FAULTA3 70 Schmitt Input PWMB0 32 Output PWMB1 33 PWMB2 34 PWMB3 37 PWMB4 38 PWMB5 39 ...
Page 33
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name ANA4 84 Input ANA5 85 ANA6 86 ANA7 Input REFH V 92 Input/ REFP Output V 91 REFMID V 90 REFN V ...
Page 34
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name CAN_TX 120 Open Drain Output TC0 111 Schmitt Input/ Output (GPIOE8) Schmitt Input/ TC1 113 Output (GPIOE9) TD0 107 Schmitt Input/ Output (GPIOE10) Schmitt Input/ ...
Page 35
Table 2-2 Signal and Package Information for the 128-Pin LQFP Signal Pin No. Type Name RESET 78 Schmitt Input RSTO 77 Output EXTBOOT Internal Schmitt Ground Input EMI_MODE Internal Schmitt Ground Input Freescale Semiconductor Preliminary State During Signal Description Reset ...
Page 36
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
Page 37
The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL R Z CLKMODE ...
Page 38
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal EXTAL XTAL R z CL1 CL2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset ...
Page 39
RAM and Flash memories are used in both spaces. This section provides memory maps for: • Program Address Space, including the Interrupt Vector Table • Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for ...
Page 40
Table 4-2 OMR MB/MA Value at Reset OMR MB = OMR MA = Flash Secured EXTBOOT Pin 2,3 State Information in shaded areas not applicable to 56F8345/56F8145. 2. This bit is only configured at reset. If the ...
Page 41
Table 4-4 Program Memory Map at Reset Mode 0 ( Begin/End Internal Boot Address Internal Boot 16-Bit External Address Bus P:$1F FFFF External Program Memory P:$10 0000 P:$0F FFFF P:$03 0000 P:$02 FFFF On-Chip Program RAM P:$02 F800 ...
Page 42
JMP instructions. All other entries must contain JSR instructions. Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8145 device. Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level core ...
Page 43
Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level FLEXCAN 29 0-2 GPIOF 30 0-2 GPIOE 31 0-2 GPIOD 32 0-2 GPIOC 33 0-2 GPIOB 34 0-2 GPIOA 35 0-2 SPI1 38 0-2 SPI1 39 0-2 SPI0 40 ...
Page 44
Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level TMRB 60 0-2 TMRB 61 0-2 TMRB 62 0-2 TMRB 63 0-2 TMRA 64 0-2 TMRA 65 0-2 TMRA 66 0-2 TMRA 67 0-2 SCI0 68 0-2 SCI0 69 ...
Page 45
Data Map Note: Data Flash is NOT available on the 56F8145 device. Begin/End Address X:$FF FFFF EOnCE X:$FF FF00 256 locations allocated X:$FF FEFF External Memory X:$01 0000 X:$00 FFFF On-Chip Peripherals X:$00 F000 4096 locations allocated X:$00 EFFF ...
Page 46
BOOT_FLASH_START + $1FFF BOOT_FLASH_START = $02_0000 PROG_FLASH_START + $00_FFFF PROG_FLASH_START + $00_FFF7 PROG_FLASH_START + $00_FFF6 128KB PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-7 shows the page and sector sizes used within each Flash memory block on ...
Page 47
Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF FF96 OBCR (24 bits) X:$FF FF97 ...
Page 48
Table 4-9 Data Memory Peripheral Base Address Map Summary Peripheral External Memory Interface Timer A Timer B Timer C Timer D PWM A PWM B Quadrature Decoder 0 Quadrature Decoder 1 ITCN ADC A ADC B Temperature Sensor SCI #0 ...
Page 49
Table 4-10 External Memory Integration Registers Address Map Register Address Acronym Offset CSBAR 0 $0 Chip Select Base Address Register 0 CSBAR 1 $1 Chip Select Base Address Register 1 CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR ...
Page 50
Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR ...
Page 51
Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSCR Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the ...
Page 52
Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8145 device Register Acronym TMRB1_CMP2 TMRB1_CAP TMRB1_LOAD TMRB1_HOLD TMRB1_CNTR TMRB1_CTRL TMRB1_SCR TMRB1_CMPLD1 TMRB1_CMPLD2 TMRB1_COMSCR TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 ...
Page 53
Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8145 device Register Acronym TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 ...
Page 54
Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D ...
Page 55
Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8145 device Register Acronym TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 ...
Page 56
Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8145 device Register Acronym TMRD2_COMSCR TMRD3_CMP1 TMRD3_CMP2 TMRD3_CAP TMRD3_LOAD TMRD3_HOLD TMRD3_CNTR TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR Table 4-15 Pulse Width Modulator A Registers ...
Page 57
Table 4-15 Pulse Width Modulator A Registers Address Map (Continued) PWMA is NOT available in the 56F8145 device Register Acronym PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Table 4-16 Pulse Width Modulator B Registers Address Map Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA PWMB_PMOUT ...
Page 58
Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the ...
Page 59
Table 4-18 Quadrature Decoder 1 Registers Address Map (Continued) Quadrature Decoder 1 is NOT available in the 56F8145 device Register Acronym DEC1_IMR Table 4-19 Interrupt Control Registers Address Map Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR ...
Page 60
Table 4-20 Analog-to-Digital Converter Registers Address Map Register Acronym ADCA_CR1 ADCA_CR2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ...
Page 61
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_HLMT 7 ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR1 ...
Page 62
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 ADCB_LLMT 5 ADCB_LLMT 6 ADCB_LLMT 7 ADCB_HLMT 0 ADCB_HLMT 1 ADCB_HLMT 2 ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ...
Page 63
Table 4-23 Serial Communication Interface 0 Registers Address Map Register Acronym SCI0_SCIBR SCI0_SCICR SCI0_SCISR SCI0_SCIDR Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register ...
Page 64
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (Continued) Register Acronym SPI1_SPDTR Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB PLLSR SHUTDOWN ...
Page 65
Table 4-29 GPIOA Registers Address Map (Continued) Register Acronym GPIOA_PPMODE GPIOA_RAWDATA Table 4-30 GPIOB Registers Address Map Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Table 4-31 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR ...
Page 66
Table 4-31 GPIOC Registers Address Map (Continued) Register Acronym GPIOC_RAWDATA Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table 4-33 GPIOE Registers Address Map Register Acronym Address ...
Page 67
Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS ...
Page 68
Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers Address Map Register Acronym FMCLKD FMMCR FMSECH FMSECL FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 68 (LVI_BASE = $00 F360) Address ...
Page 69
Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8145 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL Freescale ...
Page 70
Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8145 device Register Acronym FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW ...
Page 71
Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8145 device Register Acronym FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH ...
Page 72
Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8145 device Register Acronym FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA ...
Page 73
Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8145 device Register Acronym FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA ...
Page 74
Data Flash (NOT available in the 56F8145) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual (MC56F83xxBLUM) provides detailed information on this firmware. An application note, Production Flash Programming (AN1973), details how the Serial Bootloader program can be used ...
Page 75
Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 ...
Page 76
Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
Page 77
Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has ...
Page 78
Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD $3 IPR3 IPL W R SPI0_RCV SPI1_XMIT $4 ...
Page 79
Figure 5-2 ITCN Register Map Summary 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field ...
Page 80
Interrupt Priority Register 1 (IPR1) Base + $ Read Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It ...
Page 81
IRQ is priority level 2 • IRQ is priority level 3 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 ...
Page 82
IRQ is priority level 1 • IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This ...
Page 83
IRQ is priority level 1 • IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $ Read GPIOD GPIOE IPL IPL Write RESET Figure 5-6 ...
Page 84
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—Bits 7–6 ...
Page 85
Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI 0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 ...
Page 86
GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) ...
Page 87
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer ...
Page 88
SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
Page 89
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
Page 90
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not ...
Page 91
Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
Page 92
IRQ is priority level 1 • IRQ is priority level 2 5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This ...
Page 93
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.9.3 Reserved—Bits 11–10 This bit field is reserved or not ...
Page 94
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits ...
Page 95
Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
Page 96
IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits ...
Page 97
Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without ...
Page 98
Fast Interrupt 1 Match Register (FIM1) Base + $ Read Write RESET Figure 5-17 Fast Interrupt 1 Match Register (FIM1) 5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not ...
Page 99
Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined ...
Page 100
IRQ Pending 2 Register (IRQP2) Base + $ Read Write RESET Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the ...
Page 101
IRQ Pending (PENDING)—Bits 80–65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for ...
Page 102
ITCN Control Register (ICTL) Base + $ Read INT IPIC Write RESET Figure 5-26 ITCN Control Register (ICTL) 5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the ...
Page 103
IRQB State Pin (IRQB STATE)—Bit 3 This read-only bit reflects the state of the external IRQB pin. 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2 This read-only bit reflects the state of the external IRQA pin. 5.6.30.8 IRQB Edge Pin ...
Page 104
Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...
Page 105
Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and ...
Page 106
Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base ...
Page 107
Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
Page 108
Software Reset (SW RST)—Bit 4 This bit is always read as 0. Writing 1 to this field will cause the part to reset. 6.5.1.4 Stop Disable (STOP_DISABLE)—Bits 3–2 • Stop mode will be entered when the 56800E ...
Page 109
External Reset (EXTR)—Bit the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or ...
Page 110
Base + $ Read Write RESET Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID) 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID) This read-only register displays the least significant half ...
Page 111
PWMA1—Bit 14 This bit controls the pull-up resistors on the FAULTA3 pin. 6.5.6.3 CAN—Bit 13 This bit controls the pull-up resistors on the CAN_RX pin. 6.5.6.4 EMI_MODE—Bit 12 This bit controls the pull-up resistors on the EMI_MODE pin. Note: ...
Page 112
Reserved—Bit 2–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.7 CLKO Select Register (SIM_CLKOSR) The CLKO select register can be used to multiplex out any one of ...
Page 113
Clockout Disable (CLKDIS)—Bit 5 • CLKOUT output is enabled and will output the signal indicated by CLKOSEL • CLKOUT is tri-stated 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO ...
Page 114
Quad Timer Controlled SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control Pin Function GPIO Input 0 GPIO Output 0 Quad Timer Input / 1 Quad Decoder 2 Input Quad ...
Page 115
Base + $ Read Write RESET Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented read as 0 and cannot ...
Page 116
Base + $ Read EMI ADCB ADCA CAN DEC1 DEC0 Write RESET Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. ...
Page 117
Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C ...
Page 118
Pulse Width Modulator B Enable (PWMB)—Bit 1 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width ...
Page 119
Base + $ Read Write RESET Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of ...
Page 120
Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Run Active Wait Core and memory clocks disabled Stop System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals. All ...
Page 121
Some applications require the 56800E STOP and WAIT instructions to be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL), described in can be on either a permanent or temporary basis. Permanently assigned applications last only until ...
Page 122
Flash Access Blocking Mechanisms The 56F8345/56F8145 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods ...
Page 123
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in ...
Page 124
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[ Using the following equation yields a DIV value ...
Page 125
The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An ...
Page 126
Table 8-1 56F8345 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8345 Table 8-2 56F8145 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8145 ...
Page 127
Table 8-2 56F8145 GPIO Ports Configuration Available Port GPIO Port Pins in Width 56F8145 Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available ...
Page 128
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOB GPIOC 128 Reset Function 0 GPIO 1 ...
Page 129
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOD Freescale Semiconductor Preliminary Reset Function 0 GPIO ...
Page 130
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOE 130 Reset Function 0 Peripheral 1 Peripheral ...
Page 131
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOF 1. Not useful in reset configuration in ...
Page 132
In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal ...
Page 133
Table 10-1 Absolute Maximum Ratings (Continued) Characteristic Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial corresponding GPIO pin is configured as open drain. Note: Pins in italics are NOT available in the 56F8145 device. ...
Page 134
Table 10-2 56F8345/56F8145 ElectroStatic Discharge (ESD) Protection Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection ...
Page 135
TJ = Junction temperature TA = Ambient temperature Note: The 56F8145 device is guaranteed to 40MHz and specified to meet Industrial requirements only; CAN is NOT available on the 56F8145 device. Table 10-4 Recommended Operating Conditions (V = 0V, ...
Page 136
DC Electrical Characteristics Note: The 56F8145 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8145 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage V OH ...
Page 137
Table 10-6 Power-On Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below V ...
Page 138
Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 800μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200mA ...
Page 139
Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8145 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
Page 140
AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
Page 141
External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width 4 External clock input rise time 5 External clock input fall time 1. Parameters listed are guaranteed ...
Page 142
This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal ...
Page 143
The interrupt instruction fetch is visible on the pins only in Mode 3. RESET t RAZ A0–A15, D0–D15 Figure 10-4 Asynchronous Reset Timing IRQA, IRQB Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive) A0–A15 t IDM , IRQA IRQB General ...
Page 144
IW IRQA A0–A15 Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 10.9 Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master ...
Page 145
Characteristic Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-9 SPI ...
Page 146
SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 1) 146 SS is held High on master ...
Page 147
SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
Page 148
Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. ...
Page 149
Phase A (Input) Phase B (Input) Figure 10-14 Quadrature Decoder Timing 10.12 Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD TXD Pulse Width 1. Parameters listed are guaranteed by design. 2. ...
Page 150
TXD SCI receive data pin (Input) 10.13 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8145 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin ...
Page 151
Characteristic TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time 1. TCK frequency of operation must be less than 1/8 the processor rate processor clock period (nominally 1/60MHz) TCK (Input ...
Page 152
TRST (Input) 10.15 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection ...
Page 153
Table 10-23 ADC Parameters (Continued) Characteristic Uncalibrated Offset Voltage 6 Calibrated Absolute Error 7 Calibration Factor 1 7 Calibration Factor 2 Crosstalk between channels Common Mode Voltage Signal-to-noise ratio Signal-to-noise plus distortion ratio Total Harmonic Distortion Spurious Free Dynamic Range ...
Page 154
Figure 10-21 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
Page 155
Equivalent Circuit for ADC Inputs Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
Page 156
Analog Input 1 1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf 3. Equivalent resistance for the ESD isolation resistor and ...
Page 157
Table 10-24 IO Loading Coefficients at 10MHz PDU08DGZ_ME PDU04DGZ_ME Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. in the IO cells as a function ...
Page 158
Part 11 Packaging 11.1 56F8345 Package and Pin-Out Information This section contains package and pin-out information for the 56F8345. This device comes in a 128-pin Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and ...
Page 159
INDEX0 HOME0 PIN DD_IO CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 V 4 CAP V DD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 V SS GPIOF0 GPIOF1 GPIOF2 V DD_IO GPIOF3 GPIOB0 GPIOB1 GPIOB2 ...
Page 160
Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No CLKO 7 TXD0 8 RXD0 9 PHASEA1 10 PHASEB1 11 INDEX1 12 HOME1 CAP 14 ...
Page 161
Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 32 PWMB0 11.2 56F8145 Package and Pin-Out Information This section contains package and pin-out information for the 56F8145. This device comes in a ...
Page 162
INDEX0 HOME0 PIN DD_IO CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 V 4 CAP V DD_IO GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 V SS GPIOF0 GPIOF1 GPIOF2 V DD_IO GPIOF3 GPIOB0 GPIOB1 GPIOB2 ...
Page 163
Table 11-2 56F8145 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 INDEX0 2 HOME0 DD_IO CLKO 7 TXD0 8 RXD0 9 SCLK1 10 MOSI1 ...
Page 164
... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8345 Rev. 17 01/2007 ...