MC56F8345 Freescale Semiconductor, Inc, MC56F8345 Datasheet - Page 6
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MC56F8345
Manufacturer Part Number
MC56F8345
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8345.pdf
(164 pages)
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Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 7
Part 2: Signal/Connection Descriptions . . 17
Part 3: On-Chip Clock Synthesis (OCCS) . . 36
Part 4: Memory Map. . . . . . . . . . . . . . . . . . . 38
Part 5: Interrupt Controller (ITCN) . . . . . . . 74
Part 6: System Integration Module (SIM .) 104
Part 7: Security Features . . . . . . . . . . . . . 121
6
1.1. 56F8345/56F8145 Features . . . . . . . . . . . . . . 7
1.2. Device Description . . . . . . . . . . . . . . . . . . . . . .9
1.3. Award-Winning Development Environment . .11
1.4. Architecture Block Diagram . . . . . . . . . . . . . . 12
1.5. Product Documentation . . . . . . . . . . . . . . . . . 16
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . . 16
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2. External Clock Operation . . . . . . . . . . . . . . . .36
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1. Introductio . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . . 41
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . . 45
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . . 46
4.7. Peripheral Memory Mapped Registers . . . . . 47
4.8. Factory Programmed Memory. . . . . . . . . . . . 73
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3. Functional Description . . . . . . . . . . . . . . . . . . 74
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 76
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . . 76
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . .77
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . 105
6.4. Operating Mode Register . . . . . . . . . . . . . . 105
6.5. Register Descriptions . . . . . . . . . . . . . . . . . 106
6.6. Clock Generation Overview . . . . . . . . . . . . .119
6.7. Power-Down Modes Overview . . . . . . . . . . 119
6.8. Stop and Wait Mode Disable Function . . . . 120
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.1. Operation with Security Enabled . . . . . . . . .121
7.2. Flash Access Blocking Mechanisms . . . . . . 122
56F8345 Technical Data, Rev. 17
Table of Contents
Part 8: General Purpose Input/Output
Part 9: Joint Test Action Group (JTAG) . . 131
Part 10: Specifications. . . . . . . . . . . . . . . . 131
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 158
Part 12: Design Considerations . . . . . . . . 163
Part 13: Ordering Information . . . . . . . . . . 163
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 125
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . . 125
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 131
10.1. General Characteristics. . . . . . . . . . . . . . . 131
10.2. DC Electrical Characteristics. . . . . . . . . . . 136
10.3. AC Electrical Characteristics . . . . . . . . . . . 140
10.4. Flash Memory Characteristics. . . . . . . . . . 140
10.5. External Clock Operation Timing . . . . . . . 141
10.6. Phase Locked Loop Timing. . . . . . . . . . . . 141
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 142
10.8. Reset, Stop, Wait, Mode Select, and
10.9. Serial Peripheral Interface (SPI) Timing . . 144
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 148
10.11. Quadrature Decoder Timing . . . . . . . . . . 148
10.12. Serial Communication Interface
10.13. Controller Area Network (CAN) Timing . . 150
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 150
10.15. Analog-to-Digital Converter
10.16. Equivalent Circuit for ADC Inputs . . . . . . 155
10.17. Power Consumption . . . . . . . . . . . . . . . . 156
11.1. 56F8345 Package and Pin-Out
11.2. 56F8145 Package and Pin-Out
12.1. Thermal Design Considerations . . . . . . . . . 163
12.2. Electrical Design Considerations . . . . . . . 163
12.3. Power Distribution and I/O Ring
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 125
Interrupt Timing . . . . . . . . . . . . . . . 142
(SCI) Timing . . . . . . . . . . . . . . . . . 149
(ADC) Parameters . . . . . . . . . . . . 152
Information . . . . . . . . . . . . . . . . . . 158
Information . . . . . . . . . . . . . . . . . . 161
Implementation . . . . . . . . . . . . . . . 163
Freescale Semiconductor
Preliminary