MC56F8345 Freescale Semiconductor, Inc, MC56F8345 Datasheet - Page 104
![no-image](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_sml.jpg)
MC56F8345
Manufacturer Part Number
MC56F8345
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8345.pdf
(164 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8345MFG60
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Company:
Part Number:
MC56F8345MFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8345MFGE
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC56F8345VFGE
Manufacturer:
Freescale Semiconductor
Quantity:
1 985
Company:
Part Number:
MC56F8345VFGE
Manufacturer:
MOTOLOLA
Quantity:
245
Company:
Part Number:
MC56F8345VFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
104
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be done
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be 3 x 32
clocks (phased release of reset) for reset, except for POR, which is 2
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
explicitly
56F8345 Technical Data, Rev. 17
21
clock cycles.
Freescale Semiconductor
Preliminary