DSPIC30F2012 Microchip Technology Inc., DSPIC30F2012 Datasheet - Page 115

• Manufacturer Part Number: DSPIC30F2012
• Description: Dspic30f2011/2012/3012/3013 High-performance Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
16.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 16-1.
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
FIGURE 16-3:
© 2006 Microchip Technology Inc.
the recommended circuit shown in Figure 16-2.
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
(14 + 1) x 200,000
200 KSPS CONFIGURATION
GUIDELINE
Note: C
1
Legend: C
VA
PIN
REF
Rs
12-BIT A/D CONVERTER ANALOG INPUT MODEL
value depends on device package and is not tested. Effect of C
+ and V
V
I leakage
R
R
C
ANx
T
PIN
IC
SS
HOLD
C
= 334 ns
PIN
REF
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
- pins following
dsPIC30F2011/2012/3012/3013
AD
V
by
DD
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
IC
500 nA
250
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 16-1 for code
example.
16.8
The analog input model of the 12-bit ADC is shown in
Figure 16-3. The total sampling time for the A/D is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
ance combine to directly affect the time required to
charge the capacitor C
ance of the analog sources must therefore be small
enough to fully charge the holding capacitor within the
chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the ADC, the max-
imum recommended source impedance, R
After the analog input channel is selected (changed),
this sampling function must be completed prior to start-
ing the conversion. The internal holding capacitor will
be in a discharged state prior to each sample opera-
tion.
IC
), and the internal sampling switch (R
Sampling
Switch
A/D Acquisition Requirements
R
SS
PIN
R
negligible if Rs
SS
V
SS
HOLD
C
= DAC capacitance
= 18 pF
S
HOLD
), the interconnect impedance
3 k
HOLD
) must be allowed to fully
. The combined imped-
AD
selection in conjunc-
2.5 k .
DS70139E-page 113
S
SS
, is 2.5 k .
) imped-