DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 315

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

INDEX
A
A/D Converter ................................................................... 231
AC Characteristics ............................................................ 273
AC-Link Mode Operation .................................................. 224
ADC Module
Alternate Vector Table (AIVT) ............................................. 79
Arithmetic Logic Unit (ALU)................................................. 23
Assembler
Automatic Clock Stretch.................................................... 171
B
Barrel Shifter ....................................................................... 27
Bit-Reversed Addressing .................................................... 60
Block Diagrams
C
C Compilers
Clock Switching................................................................. 142
Code Examples
Code Protection ........................................................ 245, 251
© 2007 Microchip Technology Inc.
DMA .......................................................................... 231
Initialization ............................................................... 231
Key Features............................................................. 231
Internal RC Accuracy ................................................ 275
Load Conditions ........................................................ 273
16-bit Mode ............................................................... 224
20-bit Mode ............................................................... 225
ADC11 Register Map .................................................. 45
ADC2 Register Map .................................................... 45
MPASM Assembler................................................... 262
Receive Mode ........................................................... 171
Transmit Mode .......................................................... 171
Example ...................................................................... 61
Implementation ........................................................... 60
Sequence Table (16-Entry)......................................... 61
16-bit Timer1 Module ................................................ 147
A/D Module ....................................................... 232, 233
Connections for On-Chip Voltage Regulator............. 249
DCI Module ............................................................... 218
Device Clock ..................................................... 135, 137
DSP Engine ................................................................ 24
dsPIC33F .................................................................... 14
dsPIC33F CPU Core................................................... 18
ECAN Module ........................................................... 188
Input Capture ............................................................ 155
Output Compare ....................................................... 159
PLL............................................................................ 137
Reset System.............................................................. 73
Shared Port Structure ............................................... 145
SPI ............................................................................ 162
Timer2 (16-bit) .......................................................... 151
Timer2/3 (32-bit) ....................................................... 150
UART ........................................................................ 179
Watchdog Timer (WDT) ............................................ 250
MPLAB C18 .............................................................. 262
MPLAB C30 .............................................................. 262
Enabling .................................................................... 142
Sequence.................................................................. 142
Erasing a Program Memory Page............................... 71
Initiating a Programming Sequence............................ 72
Loading Write Buffers ................................................. 72
Port Write/Read ........................................................ 146
PWRSAV Instruction Syntax..................................... 143
dsPIC33FJXXXGPX06/X08/X10
Configuration Bits ............................................................. 245
Configuration Register Map .............................................. 245
Configuring Analog Port Pins............................................ 146
CPU
CPU Clocking System ...................................................... 136
Customer Change Notification Service............................. 317
Customer Notification Service .......................................... 317
Customer Support............................................................. 317
D
Data Accumulators and Adder/Subtractor .......................... 25
Data Address Space........................................................... 32
Data Converter Interface (DCI) Module ............................ 217
DC Characteristics............................................................ 266
DCI
Description (Table) ................................................... 246
Control Register.......................................................... 20
Options ..................................................................... 136
Selection................................................................... 136
Data Space Write Saturation ...................................... 27
Overflow and Saturation ............................................. 25
Round Logic ............................................................... 26
Write Back .................................................................. 26
Alignment.................................................................... 32
Memory Map for dsPIC33F Devices with
Memory Map for dsPIC33F Devices with
Memory Map for dsPIC33F Devices with
Near Data Space ........................................................ 32
Software Stack ........................................................... 57
Width .......................................................................... 32
I/O Pin Input Specifications ...................................... 270
I/O Pin Output Specifications.................................... 271
Idle Current (I
Idle Current (I
Operating Current (I
Power-Down Current (I
Program Memory...................................................... 272
Temperature and Voltage Specifications.................. 266
Bit Clock Generator .................................................. 221
Buffer Alignment with Data Frames.......................... 223
Buffer Control ........................................................... 217
Buffer Data Alignment .............................................. 217
Buffer Length Control ............................................... 222
CSDO Mode Bit ........................................................ 224
Data Justification Control Bit .................................... 222
Device Frequencies for Common Codec CSCK
Digital Loopback Mode ............................................. 224
Frame Sync Generator ............................................. 219
Frame Sync Mode Control Bits................................. 219
Interrupts .................................................................. 224
Introduction............................................................... 217
Master Frame Sync Operation ................................. 219
Module Enable.......................................................... 219
Operation.................................................................. 219
Operation During CPU Idle Mode............................. 224
Operation During CPU Sleep Mode ......................... 224
Receive Slot Enable Bits .......................................... 222
Receive Status Bits .................................................. 223
Sample Clock Edge Control Bit ................................ 222
Slave Frame Sync Operation ................................... 220
16 KBs RAM ....................................................... 34
30 KBs RAM ....................................................... 35
8 KBs RAM ......................................................... 33
Frequencies (Table) ......................................... 221
DOZE
IDLE
) .................................................... 268
) .................................................. 269
DD
) ............................................ 267
PD
)........................................ 268
DS70286A-page 311